MAX17080 데이터 시트보기 (PDF) - Maxim Integrated
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MAX17080 Datasheet PDF : 48 Pages
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AMD 2-/3-Output Mobile Serial
VID Controller
Pin Description (continued)
PIN
NAME
FUNCTION
Open-Drain Power-Good Output. PWRGD is the wired-OR open-drain output of all three SMPS
outputs.
PWRGD is forced high impedance whenever the slew-rate controller is active (output voltage
transitions).
During startup, PWRGD is held low for an additional 20µs after the MAX17080 reaches the startup
boot voltage set by the SVC and SVD pins. The MAX17080 stores the boot VID when PWRGD first
goes high. The stored boot VID is cleared by rising SHDN.
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PWRGD PWRGD is forced low in shutdown.
When SMPS is in pulse-skipping mode, the upper PWRGD threshold comparator for the respective
SMPS is blanked during a downward VID transition. The upper PWRGD threshold comparator is re-
enabled once the output is in regulation (Figure 5).
If PGD_IN goes low anytime after the boot sequence, PWRGD is forced low during the time when
any one of the three internal DACs is slewing from the current VID to the stored boot VID plus an
additional 20µs.
21
DH2
SMPS2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.
22
LX2
SMPS2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
Also used as an input to SMPS2’s zero-crossing comparator.
23
BST2
Boost Flying Capacitor Connection for the DH2 High-Side Gate Driver. An internal switch between
VDD and BST2 charges the flying capacitor during the time the low-side FET is on.
SMPS2 Low-Side Gate-Driver Output. DL2 swings from GND2 to VDD. DL2 is forced low in shutdown.
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DL2
DL2 is also forced high when an output overvoltage fault is detected. DL2 is forced low in skip
mode after an inductor current zero crossing (GND2 - LX2) is detected.
Supply Voltage Input for the DL_ Drivers. VDD is also the supply voltage used to internally recharge
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VDD
the BST_ flying capacitors during the off-time. Connect VDD to the 4.5V to 5.5V system supply
voltage. Bypass VDD to GND with a 2.2µF or greater ceramic capacitor.
SMPS1 Low-Side Gate-Driver Output. DL1 swings from GND1 to VDD. DL1 is forced low in shutdown.
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DL1
DL1 is also forced high when an output overvoltage fault is detected. DL1 is forced low in skip
mode after an inductor current zero crossing (GND1 - LX1) is detected.
27
BST1
Boost Flying Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between
VDD and BST1 charges the flying capacitor during the time the low-side FET is on.
28
LX1
SMPS1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
Also used as an input to SMPS1’s zero-crossing comparator.
29
DH1
SMPS1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.
30
VRHOT
Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes
below 1.5V (30% of VCC). VRHOT is high impedance in shutdown.
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC
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THRM and GND) to THRM. Select the components so the voltage at THRM falls below 1.5V (30% of VCC)
at the desired high temperature.
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1µF minimum. A
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VCC
VCC UVLO event that occurs while the IC is functioning is latched, and can only be cleared by
cycling VCC power or by toggling SHDN.
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