MAX17080 데이터 시트보기 (PDF) - Maxim Integrated
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MAX17080 Datasheet PDF : 48 Pages
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AMD 2-/3-Output Mobile Serial
VID Controller
Pin Description (continued)
PIN
NAME
FUNCTION
SMPS2 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS2
internally connects to a transconductance amplifier that fine tunes the output voltage—
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GNDS2 compensating for voltage drops from the SMPS ground to the load ground.
Connect GNDS1 or GNDS2 above 0.9V combined-mode operation (unified core). When GNDS2 is
pulled above 0.9V, GNDS1 is used as the remote ground-sense input.
Output of the Voltage-Positioning Transconductance Amplifier for SMPS2. The R and C network
between this pin and the positive side of the remote-sensed output voltage sets the transient AC
droop:
RDROOP_AC2
=
RFBAC2 × RFBDC2
RFBAC2 + RFBDC2 + RFB2
ZCFB2
× RSENSE2
× Gm(FBAC2)
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FBAC2
where RDROOP_AC2 is the transient (AC) voltage-positioning slope that provides an acceptable
trade-off between stability and load-transient response, Gm(FBAC2) = 2mS (typ), RSENSE2 is the
value of the current-sense element that is used to provide the (CSP2, CSN2) current-sense voltage,
ZCFB2 is the impedance of CFB2.
FBAC2 is high impedance in shutdown.
Feedback-Sense Input for SMPS2. Connect a resistor RFBDC2 between FBDC2 and the positive side
of the feedback remote sense, and a capacitor from FBAC2 to couple the AC ripple from FBAC2 to
FBDC2. An integrator on FBDC2 corrects for output ripple and ground-sense offset.
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FBDC2 To enable a DC load-line less than the AC load-line, add a resistor from FBAC2 to FBDC2.
To enable a DC load-line equal to the AC load-line, short FBAC2 to FBDC2. See the Core Steady-
State Voltage Positioning (DC Droop) section.
FBDC2 is high impedance in shutdown.
Negative Current-Sense Input for SMPS2. Connect to the negative side of the output current-sensing
resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current
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CSN2
sensing.
A 20 discharge FET is enabled from CSN2 to PGND when the SMPS2 is shut down.
Positive Current-Sense Input for SMPS2. Connect to the positive side of the output current-sensing
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CSP2 resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current
sensing.
System Power-Good Input.
PGD_IN is low when SHDN first goes high. The MAX17080 decodes the 2 SVI bits to determine the
boot voltage. The SVI bits can be changed dynamically during this time while PGD_IN remains low
and PWRGD is still low.
PGD_IN goes high after the MAX17080 reaches the boot voltage. This indicates that the SVI block
is active, and the MAX17080 starts to respond to the SVI commands. The MAX17080 stores the
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PGD_IN boot VID when PWRGD first goes high. The stored boot VID is cleared by rising SHDN.
After PGD_IN has gone high, if at any time PGD_IN goes low, the MAX17080 regulates to the
previously stored boot VID. PWRGD is forced low until the internal DAC reaches the stored boot VID
plus an additional 20µs. The slew rate during this transition is set by the resistor between the TIME
and GND pins.
The subsequent rising edge of PGD_IN does not change the stored VID.
PWRGD is independent of PGD_IN.
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