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M80C287

80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION

Intel 

M80C287

In M8086 M8087 systems WAIT instructions may

be required to achieve synchronization of both com-

mands and operands In M80C287 systems howev-

er WAIT instructions are required only for operand

synchronization namely after NPX stores to memo-

ry (except FSTSW and FSTCW) or load from memo-

ry (In M80C286 M80C287 systems WAIT is re-

quired before FLDENV and FRSTOR with other

CPU’s WAIT is not required in these cases ) Used

this way WAIT ensures that the value has already

been written or read by the NPX before the CPU

reads or changes the value

Once it has started to execute a numerics instruction

and has transferred the operands from the CPU the

M80C287 can process the instruction in parallel with

and independent of the host CPU When the NPX

detects an exception it asserts the ERROR signal

which causes a CPU interrupt

Bus Operation

With respect to bus interface the M80C287 is fully

asynchronous with the CPU even when it operates

from the same clock source as the CPU The CPU

initiates a bus cycle for the NPX by activating both

NPS1 and NPS2 the NPX select signals During the

CLK period in which NPS1 and NPS2 are activated

the M80C287 also examines the NPRD and NPWR

input signals to determine whether the cycle is a

read or a write cycle and examines the CMD0 and

CMD1 inputs to determine whether an opcode oper-

and or control status register transfer is to occur

The M80C287 activates its BUSY output some time

after the leading edge of the NPRD or NPWR signal

Input and output data are referenced to the trailing

edges of the NPRD and NPWR signals

The M80C287 activates the PEREQ signal when it is

ready for data transfer In M80286 80C286 systems

the CPU activates PEACK when no more data trans-

fers are required which causes the M80C287 to de-

activate PEREQ halting the data transfer

M80287 M80C287 Socket

Compatibility and CPU Interfacing

In general the M80C287 can fit in existing M80287

sockets provided that the necessary connections to

VCC and VSS are made and that the clock require-

ments are met The pinouts for the M80C287 are

identical to those of the M80287 except for the pins

marked by asterisk ( ) in Figure 8 The pins marked

by asterisk are status lines for monitoring ESCAPE

instructions and bus cycles These lines are not crit-

ical for proper operation of an M80287 Note that

when the clock is fed in directly (CKM e 1) the

M80C287 requires a 50% duty cycle clock signal

whereas the M80287 requires a 33% duty cycle

Also note that with CKM e 0 the M80C287 divides

the clock input by two not by three as on the

M80287

The interface between the M80C287 and the

M80286 M80C286 CPU (illustrated in Figure 9) has

these characteristics

 The M80C287 resides on the local data bus of

the CPU

 The CPU and M80C287 share the same RESET

signals They may also share the same clock in-

put however for greatest performance an exter-

nal oscillator may be needed

 The corresponding BUSY ERROR PEREQ and

PEACK pins are connected together

 NPS2 is tied HIGH permanently while NPS1

CMD1 and CMD0 come from the latched ad-

dress pins The M80286 generates I O address-

es 00F8H 00FAH and 00FCH during NPX bus

cycles Address 00FEH is reserved

 The M80C287 NPRD and NPWR inputs are con-

nected to I O read and write signals from local

bus control logic

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