M80C287 데이터 시트보기 (PDF) - Intel

부품명

상세내역

일치하는 목록

M80C287

80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION

Intel 

M80C287

Many changes have been designed into the

M80C287 to directly support the IEEE standard in

hardware These changes result in increased per-

formance by eliminating the need for software that

supports the standard

GENERAL DIFFERENCES

The M80C287 supports only affine closure for infini-

ty arithmetic not projective closure

Operands for FSCALE and FPATAN are no longer

restricted in range (except for g %) F2XM1 and

FPTAN accept a wider range of operands

Rounding control is in effect for FLD constant

Software cannot change entries of the tag word to

values (other than empty) that differ from actual reg-

ister contents

After reset FINIT and incomplete FPREM the

M80C287 resets to zero the condition code bits C3 –

C0 of the status word

In conformance with the IEEE standard the

M80C287 does not support the special data formats

pseudozero pseudo-NaN pseudoinfinity and un-

normal

The denormal exception has a different purpose on

the M80C287 A system that uses the denormal-ex-

ception handler solely to normalize the denormal op-

erands would better mask the denormal exception

on the M80C287 The M80C287 automatically nor-

malizes denormal operands when the denormal ex-

ception is masked

EXCEPTIONS

A number of differences exist due to changes in the

IEEE standard and to functional improvements to

the architecture of the M80C287

1 When the overflow or underflow exception is

masked the M80C287 differs from the M80287

in rounding when overflow or underflow occurs

The M80C287 produces results that are consist-

ent with the rounding mode

2 When the underflow exception is masked the

M80C287 sets its underflow flag only if there is

also a loss of accuracy during denormalization

3 Fewer invalid-operation exceptions due to de-

normal operands because the instructions

FSQRT FDIV FPREM and conversions to BCD

or to integer normalize denormal operands be-

fore proceeding

4 The FSQRT FBSTP and FPREM instructions

may cause underflow because they support de-

normal operands

5 The denormal exception can occur during the

transcendental instructions and the FXTRACT

instruction

6 The denormal exception no longer takes prece-

dence over all other exceptions

7 When the denormal exception is masked the

M80C287 automatically normalizes denormal

operands The M8087 M80287 performs unnor-

mal arithmetic which might produce an unnor-

mal result

8 When the operand is zero the FXTRACT in-

struction reports a zero-divide exception and

leaves b % in ST(1)

9 The status word has a new bit (SF) that signals

when invalid-operation exceptions are due to

stack underflow or overflow

10 FLD extended precision no longer reports denor-

mal exceptions because the instruction is not

numeric

11 FLD single double precision when the operand

is denormal converts the number to extended

precision and signals the denormalized operand

exception When loading a signalling NaN FLD

single double precision signals an invalid-oper-

and exception

12 The M80C287 only generates quiet NaNs (as on

the M80287) however the M80C287 distin-

guishes between quiet NaNs and signaling

NaNs Signaling NaNs trigger exceptions when

they are used as operands quiet NaNs do not

(except for FCOM FIST and FBSTP which also

raise IE for quiet NaNs)

13 When stack overflow occurs during FPTAN and

overflow is masked both ST(0) and ST(1) con-

tain quiet NaNs The M8087 M80287 leaves the

original operand in ST(1) intact

14 When the scaling factor is g % the FSCALE

(ST(0) ST(1)) instruction behaves as follows

(ST(0) and ST(1) contain the scaled and scaling

operands respectively)

 FSCALE(0 %) generates the invalid operation

exception

 FSCALE(finite b%) generates zero with the

same sign as the scaled operand

 FSCALE(finite a %) generates -in with the

same sign as the scaled operand

The M8087 M80287 returns zero in the first

case and raises the invalid-operation exception

in the other cases

11

Share Link: