M80C287 데이터 시트보기 (PDF) - Intel

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M80C287

80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION

Intel 

M80C287

NPS1

x

1

0

0

0

0

0

0

0

0

NPS2

0

x

1

1

1

1

1

1

1

1

CMD0

x

x

0

0

1

1

0

0

1

1

Table 11 Bus Cycles Definition

CMD1

NPRD

NPWR

x

x

x

x

x

x

0

1

0

0

0

1

0

0

1

0

1

0

1

1

0

1

0

1

1

0

1

1

1

0

Bus Cycle Type

M80C287 not selected

M80C287 not selected

Opcode write to M80C287

CW or SW read from M80C287

Read data from M80C287

Write data to M80C287

Write exception pointers

Reserved

Reserved

Reserved

coder decodes the ESC instructions sent to it by the

CPU and generates controls that direct the data flow

in the FIFO It also triggers the microinstruction se-

quencer that controls execution of each instruction

If the ESC instruction is FINIT FCLEX FSTSW

FSTSW AX FSTCW FSETPM or FRSTPM the

control executes it independently of the FPU and the

sequencer The data interface and control unit is the

one that generates the BUSY PEREQ and ERROR

signals that synchronize M80C287 activities with the

CPU

FLOATING-POINT UNIT

The FPU executes all instructions that involve the

register stack including arithmetic logical transcen-

dental constant and data transfer instructions The

data path in the FPU is 84 bits wide (68 significant

bits 15 exponent bits and a sign bit) which allows

internal operand transfers to be performed at very

high speeds

Bus Cycles

The pins NPS1 NPS2 CMD0 CMD1 NPRD and

NPWR identify bus cycles for the NPX Table 11 de-

fines the types of M80C287 bus cycles

M80C287 ADDRESSING

The NPS1 NPS2 CMD0 and CMD1 signals allow

the NPX to identify which bus cycles are intended for

the NPX The NPX responds to I O cycles when the

I O address is 00F8H 00FAH 00FCH The corre-

spondence between I O addresses and control sig-

nals is defined by Table 12 To guarantee correct

operation of the NPX programs must not perform

any I O operations to these reserved port address-

es

Table 12 I O Address Decoding

I O Address

(Hexadecimal)

M80C287 Select and

Command Inputs

NPS2 NPS1 CMD1 CMD0

00F8

00FA

00FC

1

0

0

0

1

0

0

1

1

0

1

0

CPU NPX SYNCHRONIZATION

The pins BUSY PEREQ and ERROR are used for

various aspects of synchronization between the

CPU and the NPX

BUSY is used to synchronize instruction transfer

from the M80C286 CPU to the M80C287 When the

M80C287 recognizes an ESC instruction it asserts

BUSY For most ESC instructions the M80C286

CPU waits for the M80C287 to deassert BUSY be-

fore sending the new opcode

The NPX uses the PEREQ pin of the CPU to signal

that the NPX is ready for data transfer to or from its

data FIFO The NPX does not directly access mem-

ory rather the CPU provides memory access serv-

ices for the NPX Thus memory access on behalf of

the NPX always obeys the rules applicable to the

mode of the CPU whether the CPU be in real-ad-

dress mode or protected mode

Once the M80C286 CPU initiates an M80C287 in-

struction that has operands the M80C286 CPU

waits for PEREQ signals that indicate when the

M80C287 is ready for operand transfer Once all op-

erands have been transferred (or if the instruction

has no operands) the CPU continues program exe-

cution while the M80C287 executes the ESC instruc-

tion

15

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