M5M29GB/T161BWG 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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M5M29GB/T161BWG

16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

MITSUBISHI ELECTRIC  

MITSUBISHI LSIs

M5M29GB/T161BWG

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

SOFTWARE COMMAND DEFINITIONS

The device operations are selected by writing specific software

command into the Command User Interface.

Read Array Command (FFH)

The device is in Read Array mode on initial device power up and

after exit from deep powerdown, or by writing FFH to the

Command User Interface. After starting the internal operation the

device is set to the read status register mode automatically.

Read Device Identifier Command (90H)

It can normally read device identifier codes when Read Device

Identifier Code Command(90H) is written to the command latch.

Following the command write, the manufacturer code and the

device code can be read from address 0000H and 0001H,

respectively.

Read Status Register Command (70H)

The Status Register is read after writing the Read Status Register

command of 70H to the Command User Interface. Also, after

starting the internal operation the device is set to the Read Status

Register mode automatically.

The contents of Status Register are latched on the later falling

edge of OE# or CE#. So CE# or OE# must be toggled every status

read.

Clear Status Register Command (50H)

The Erase Status, Program Status and Block Status bits are set to

"1"s by the Write State Machine and can only be reset by the Clear

Status Register command of 50H. These bits indicates various

failure conditions.

C)Single Data Load to Page Buffer (74H)

/ Page Buffer to Flash (0EH/D0H)

Single data load to the page buffer is performed by writing 74H

followed by a second write specifying the column address and

data. Distinct data up to 128word can be loaded to the page

buffer by this two-command sequence. On the other hand, all of

the loaded data to the page buffer is programed simultaneously

by writing Page Buffer to Flash command of 0EH followed by the

confirm command of D0H. After completion of programing the

data on the page buffer is cleared automatically.

This command is valid for only Bank(I) alike Word Program.

Clear Page Buffer Command (55H)

Loaded data to the page buffer is cleared by writing the Clear

Page Buffer command of 55H followed by the Confirm command

of D0H. This command is valid for clearing data loaded by Single

Data Load to Page Buffer command.

Suspend/Resume Command (B0H/D0H)

Writing the Suspend command of B0H during block erase

operation interrupts the block erase operation and allows read out

from another block of memory. Writing the Suspend command of

B0H during program operation interrupts the program operation

and allows read out from another block of memory. The Bank

address is required when writing the Suspend/Resume Command.

The device continues to output Status Register data when read,

after the Suspend command is written to it. Polling the WSM

Status and Suspend Status bits will determine when the erase

operation or program operation has been suspended. At this

point, writing of the Read Array command to the CUI enables

reading data from blocks other than that which is suspended.

When the Resume command of D0H is written to the CUI,

the WSM will continue with the erase or program processes.

Block Erase / Confirm Command (20H/D0H)

Automated block erase is initiated by writing the Block Erase

command of 20H followed by the Confirm command of D0H. An

address within the block to be erased is required. The WSM

executes iterative erase pulse application and erase verify

operation.

Program Commands

A)Word Program (40H)

Word program is executed by a two-command sequence. The

Word Program Setup command of 40H is written to the

Command Interface, followed by a second write specifying the

address and data to be written. The WSM controls the program

pulse application and verify operation. The Word Program

Command is Valid for only Bank(I).

B)Page Program for Data Blocks (41H)

Page Program for Bank(I) and Bank(II) allows fast programming of

128words of data. Writing of 41H initiates the page program

operation for the Data area. From 2nd cycle to 129th cycle , write

data must be serially inputted. Address A6-A0 have to be

incremented from 00H to 7FH. After completion of data loading, the

WSM controls the program pulse application and verify operation.

DATA PROTECTION

The M5M29GB/T161BWG provides selectable block locking of

memory blocks. Each block has an associated nonvolatile lock-bit

which determines the lock status of the block. In addition, the

M5M29GB/T161BWG have a master Write Protect pin (WP1# &

WP2#) which prevents any modifications to memory blocks whose

lock-bits are set to "0", when WP1# or WP2# is low. When WP1#

& WP2# are high , all blocks can be programmed or erased

regardless of the state of the lock-bits, and the lock-bits are

cleared to "1" by erase. See the BLOCK LOCKING table on P.9 for

details.

Power Supply Voltage

When the power supply voltage (Vcc) is less than VLKO, Low VCC

Lock-Out voltage, the device is set to the Read-only mode.

Regarding DC electrical characteristics of VLKO, see P.9

A delay time of 2 us is required before any device operation is

initiated. The delay time is measured from the time Vcc reaches

Vccmin (2.7V).

During power up, RP#=GND is recommended. Falling in Busy

status is not recommended for possibility of damaging the device.

MEMORY ORGANIZATION

The M5M29GB/T161BWG has one 16Kword boot block, seven

16Kword parameter blocks, for Bank(I) and twenty-eight 32Kword

main blocks for Bank(II). A block is erased independently of other

blocks in the array.

4

Sep.1999. Rev4.0

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