M38504M6-200FP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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M38504M6-200FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

3850 Group (Spec. H)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[MISRG (MISRG)] 003816

MISRG consists of three control bits (bits 1 to 3) for middle-speed

mode automatic switch and one control bit (bit 0) for oscillation

stabilizing time set after STP instruction released.

By setting the middle-speed mode automatic switch start bit to “1”

while operating in the low-speed mode and setting the middle-

speed mode automatic switch set bit to “1”, XIN oscillation

automatically starts and the mode is automatically switched to the

middle-speed mode.

b7

b0

MISRG

(MISRG : address 003816)

Oscillation stabilizing time set after STP instruction

released bit

0: Automatically set “0116” to Timer 1,

“FF16” to Prescaler 12

1: Automatically set nothing

Middle-speed mode automatic switch set bit

0: Not set automatically

1: Automatic switching enable

Middle-speed mode automatic switch wait time set bit

0: 4.5 to 5.5 machine cycles

1: 6.5 to 7.5 machine cycles

Middle-speed mode automatic switch start bit

(Depending on program)

0: Invalid

1: Automatic switch start

Not used (return “0” when read)

Note: When the mode is automatically switched from the low-speed mode to

the middle-speed mode, the value of CPU mode register (address 003B16)

changes.

Fig. 41 Structure of MISRG

XCIN

XCOUT

“1” “0”

Port XC

switch bit

XIN

XOUT

Main clock division ratio

selection bits (Note 1)

Low-speed mode

1/2

1/4 1/2

High-speed or

middle-speed

mode

Prescaler 12

FF16

Timer 1

Reset or

0116

STP instruction

(Note 2)

Main clock stop bit

Main clock division ratio

selection bits (Note 1)

Middle-speed mode

High-speed or

low-speed mode

Timing φ (internal clock)

QS

R

STP instruction

SQ

WIT instruction

R

QS

R

STP instruction

Reset

Interrupt disable flag l

Interrupt request

Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.

When low-speed mode is selected, set port Xc switch bit (b4) to “1”.

2: When bit 0 of MISRG = “0”

Fig. 42 System clock generating circuit block diagram (Single-chip mode)

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