M37640E8FP 데이터 시트보기 (PDF) - Mitsumi

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M37640E8FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

Ver 1.4

MITSUBISHI MICROCOMPUTERS

7640 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

1.14.2 Port Control Register (PTC)

1.14.3 Port P2 Pull-up Control Register (PUP2)

This device is equipped with a port control register to

turn on and off the slew rate control and to control the

input levels for Port P2 and the MBI pins (see Figure

1.22).

This device is equipped with internal pull ups on Port

P2 that can be enabled by software. Each bit of the

pull-up control register controls a corresponding pin of

Port P2. The pull-up control register pulls up the port

when the port is in input mode. The value of the pull-

up control regsiter has no effect when the port is in

output mode (see Figure 1.23).

MSB

7

PTC7

PTC6 PTC5

PTC4 PTC3

PTC2

PTC1

PTC0

LSB Address: 001016

0 Access: R/W

Reset: 0016

PTC0

PTC1

PTC2

PTC3

PTC4

PTC5

PTC6

PTC7

Slew Rate Control Bit Ports P0-P3 (bit 0)

0: Disabled

1: Enabled

Slew Rate Control Bit Port P4 (bit 1)

0: Disabled

1: Enabled

Slew Rate Control Bit Port P5 (bit 2)

0: Disabled

1: Enabled

Slew Rate Control Bit Port P6 (bit 3)

0: Disabled

1: Enabled

Slew Rate Control Bit Port P7 (bit 4)

0: Disabled

1: Enabled

Slew Rate Control Bit Port P8 (bit 5)

0: Disabled

1: Enabled

Port P2 Input Level Select Bit (bit 6)

0 : Reduced VIHL Level Input

1 : CMOS level input

Master Bus Input Level Select Bit (bit 7)

0 : CMOS level input

1 : TTL level input

Fig. 1.22. Port Control Register (PTC)

MSB

7

PUP27

PUP26 PUP25

PUP24

PUP23

PUP22

PUP21

PUP20

LSB

0

Address: 001216

Access: R/W

Reset: 0016

PUP20

PUP21

PUP22

PUP23

PUP24

PUP25

PUP26

PUP27

Pull-up Control for Port P2 (bit 0)

0: Disabled

1: Enabled

Pull-up Control for Port P2 (bit 1)

0: Disabled

1: Enabled

Pull-up Control for Port P2 (bit 2)

0: Disabled

1: Enabled

Pull-up Control for Port P2 (bit 3)

0: Disabled

1: Enabled

Pull-up Control for Port P2 (bit 4)

0: Disabled

1: Enabled

Pull-up Control for Port P2 (bit 5)

0: Disabled

1: Enabled

Pull-up Control for Port P2 (bit 6)

0: Disabled

1: Enabled

Pull-up Control for Port P2 (bit 7)

0: Disabled

1: Enabled

Fig. 1.23. Pull-up Control Register (PUP2)

25

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