M37640E8FP 데이터 시트보기 (PDF) - Mitsumi

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M37640E8FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

Ver 1.4

MITSUBISHI MICROCOMPUTERS

7640 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

1.14 INPUT AND OUTPUT PORTS

Table 1.5. Input and Output Ports

Pin

P00 – P07

P10 – P17

P20 – P27

P30 – P37

P40

P41

P42

P43

P44

P50

P51

P52

P53

P54

P55

P56

P57

P60– P67

P70

P71

P72

P73

P74

P80

P81

P82

P83

P84

P85

P86

P87

Name

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Input/

Output

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

I/O

Format

CMOS I/O

port

CMOS I/O

port

CMOS I/O

port

CMOS I/O

port

CMOS I/O

port

CMOS I/O

port

CMOS I/O

port

CMOS I/O

port

CMOS I/O

port

Non-Port

Function

Address Bus

Address Bus

Data Bus

Control signal I/O

Expanded Data Memory

Access

External Interrupt Input

(INT0)

External Interrupt Input

(INT1)

External Interrupt Input

(CNTR0)

External Interrupt Input

(CNTR1)

Xcin

Xcout or Tout

OBF0 Output

IBF0 Output

S0 Input

A0 Input

R(E) Input

W(R/W) Input

Master CPU data bus

SOF Output

HOLD

S1 Input

IBF1 Output

OBF1 Output

UTXD2/SRDY

URXD2/SCLK

CTS2/STXD

RTS2/SRXD

UTXD1

URXD1

CTS1

RTS1

Related

SFR’s

CPU Mode Register

CPU Mode Register

CPU Mode Register

CPU Mode Register

CPU Mode Register

Interrupt Edge

Selection Register

Interrupt Edge

Selection Register

Timer X Mode

Register

Timer Y Mode

Register

CPU Mode Register

CPU Mode Register

or T123 Mode

Register

MBI Interface

MBI Interface

MBI Interface

MBI Interface

MBI Interface

MBI Interface

MBI Interface

USB Interface

CPU Mode Register

MBI Interface

MBI Interface

MBI Interface

UART Mode

Register/SIO Mode

Register

UART Mode

Register/SIO Mode

Register

UART Mode

Register/SIO Mode

Register

UART Mode

Register/SIO Mode

Register

UART Mode

Register

UART Mode

Register

UART Mode

Register

UART Mode

Register

Ref. Number

Fig. 1.15

Fig. 1.15

Fig. 1.15

Fig. 1.15

Fig. 1.16

Fig. 1.16

Fig. 1.16

Fig. 1.16

Fig. 1.16

Fig. 1.17

Fig. 1.17

Fig. 1.17

Fig. 1.17

Fig. 1.17

Fig. 1.17

Fig. 1.17

Fig. 1.17

Fig. 1.18

Fig. 1.19

Fig. 1.19

Fig. 1.19

Fig. 1.19

Fig. 1.19

Fig. 1.20

Fig. 1.20

Fig. 1.21

Fig. 1.21

Fig. 1.21

Fig. 1.22

Fig. 1.22

Fig. 1.22

17

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