EBS52UC8APSA-75 데이터 시트보기 (PDF) - Elpida Memory, Inc
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EBS52UC8APSA-75 Datasheet PDF : 14 Pages
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EBS52UC8APSA
Pin Capacitance (TA = +25°C, VDD = 3.3V ± 0.3V)
Parameter
Input capacitance
Data input/output capacitance
Symbol
CI1
CI2
CI3
CI4
CI5
CI6
CI/O1
Pins
Address
/RAS, /CAS, /WE
CKE
/CS
CLK
DQMB
DQ
max.
46
50
60
30
32
8
12
Unit
Notes
pF
pF
pF
pF
pF
pF
pF
AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ± 0.3V, VSS = 0V) (SDRAM device specification)
-7A/7AL
-75/75L
Parameter
Symbol min.
max.
min.
max.
Unit
Notes
System clock cycle time
(CL = 2)
(CL = 3)
tCK 7.5
—
10
—
ns
1
tCK 7.5
—
7.5
—
ns
CLK high pulse width
tCH 2.5
—
2.5
—
ns
1
CLK low pulse width
tCL 2.5
—
2.5
—
ns
1
Access time from CLK
tAC —
5.4
—
5.4
ns
1, 2
Data-out hold time
tOH 2.7
—
2.7
—
ns
1, 2
CLK to Data-out low impedance
tLZ 1
—
1
—
ns
1, 2, 3
CLK to Data-out high impedance
tHZ —
5.4
—
5.4
ns
1, 4
Input setup time
tSI
1.5
—
1.5
—
ns
1
Input hold time
tHI
0.8
—
0.8
—
ns
1
Ref/Active to Ref/Active command period tRC 60
—
67.5
—
ns
1
Active to Precharge command period tRAS 45
120000 45
120000 ns
1
Active command to column command
(same bank)
tRCD 15
—
20
—
ns
1
Precharge to active command period tRP 15
—
20
—
ns
1
Write recovery or data-in to precharge
lead time
tDPL
15
—
15
—
ns
1
Last data into active latency
tDAL
2CLK +
15ns
—
2CLK +
20ns
—
Active (a) to Active (b) command period tRRD 15
—
15
—
ns
1
Transition time (rise and fall)
tT
0.5
5
0.5
5
ns
Refresh period
(8192 refresh cycles)
tREF —
64
—
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
2. Access time is measured at 1.4V. Load condition is CL = 50pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Data Sheet E0240E20 (Ver. 2.0)
9
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