LT3030HFE-PBF 데이터 시트보기 (PDF) - Linear Technology
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LT3030HFE-PBF Datasheet PDF : 22 Pages
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LT3030
Pin Functions (QFN/TSSOP)
OUT1, OUT2 (Pins 1, 2, 7, 8/Pins 3, 4, 7, 8): Output. The
OUT1/OUT2 pins supply power to the loads. A minimum
10μF/3.3μF output capacitor prevents oscillations on
OUT1/OUT2. Applications with large output load transients
require larger values of output capacitance to limit peak
voltage transients. See the Applications Information sec-
tion for more on output capacitance and on reverse output
characteristics.
GND (Pins 3, 4, 5, 6, 11, 12, 13, 18, 19, 24, 25, 26,
Exposed Pad Pin 29/Pins 5, 6, 15, 16, Exposed Pad Pin
21): Ground. The exposed pad (backside) of the QFN and
TSSOP packages is an electrical connection to GND. To
ensure proper electrical and thermal performance, sol-
der the exposed pad to the PCB ground and tie directly
to GND pins. Connect the bottom of the output voltage
setting resistor divider directly to GND for optimum load
regulation performance.
IN1, IN2 (Pins 20, 21, 16, 17/Pins 17, 18, 13, 14): In-
put. The IN1/IN2 pins supply power to each channel. The
LT3030 requires a bypass capacitor at the IN1/IN2 pins
if located more than six inches away from the main input
filter capacitor. Include a bypass capacitor in battery-
powered circuits, as a battery’s output impedance rises
with frequency. A bypass capacitor in the range of 1μF to
10μF suffices. The LT3030’s design withstands reverse
voltages on the IN pins with respect to ground and the
OUT pins. In the case of a reversed input, which occurs
if a battery is plugged in backwards, the LT3030 acts as
if a diode is in series with its input. No reverse current
flows into the LT3030 and no reverse voltage appears at
the load. The device protects itself and the load.
PWRGD1, PWRGD2 (Pins 22, 15/Pins 19, 12): Power
Good. The PWRGD flag is an open-collector flag to indicate
that the output voltage has increased above 90% of the
nominal output voltage. There is no internal pull-up on
this pin; a pull-up resistor must be used. The PWRGD pin
changes state from an open-collector pull-down to high
impedance after the output increases above 90% of the
nominal voltage. The maximum pull-down current of the
PWRGD pin in the low state is 100μA.
SHDN1, SHDN2 (Pins 23, 14/Pins 20, 11): Shutdown.
Pulling the SHDN1 or SHDN2 pin low puts its correspond-
ing LT3030 channel into a low power state and turns its
output off. The SHDN1 and SHDN2 pins are completely
independent of each other, and each SHDN pin only affects
operation on its corresponding channel. Drive the SHDN1
and SHDN2 pins with either logic or an open collector/drain
with pull-up resistors. The resistors supply the pull-up
current to the open collectors/drains and the SHDN1 or
SHDN2 current, typically less than 1μA. If unused, con-
nect SHDN1 and SHDN2 to their corresponding IN pins.
Each channel will be in its low power shutdown state if its
corresponding SHDN pin is not connected.
ADJ1, ADJ2 (Pins 27, 10/Pins 1, 10): Adjust Pin. These
are the error amplifier inputs. These pins are internally
clamped to ±9V. A typical input bias current of 30nA flows
into the pins (see curve of ADJ1/ADJ2 Pin Bias Current vs
Temperature in the Typical Performance Characteristics
section). The ADJ1 and ADJ2 pin voltages are 1.220V
referenced to ground and the output voltage range is
1.220V to 19.5V.
BYP1, BYP2 (Pins 28, 9/Pins 2, 9): Bypass. Connecting
a capacitor between OUT and BYP of a respective chan-
nel bypasses the LT3030 reference to achieve low noise
performance, improve transient response and soft-start
the output. Internal circuitry clamps the BYP1/BYP2 pins
to ±0.6V (one VBE) from ground. A small capacitor from
the corresponding output to this pin bypasses the refer-
ence to lower the output voltage noise. Using a maximum
value of 10nF reduces the output voltage noise to a typical
20μVRMS over a 10Hz to 100kHz bandwidth. If not used,
this pin must be left unconnected.
For more information www.linear.com/LT3030
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