HYS72V4120GU-10 데이터 시트보기 (PDF) - Siemens AG

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HYS72V4120GU-10

3.3V 4M x 64-Bit 2 BANK SDRAM Module 3.3V 4M x 72-Bit 2 BANK SDRAM Module 168 pin unbuffered DIMM Modules

Siemens AG 

HYS64(72)V4120GU-10

4M x 64/72 SDRAM-Module

Parameter

CAS to CAS delay time (same bank)

Symbol

Limit Values

-10

min

max

tCCD

1

–

Unit Note

CLK

Refresh Cycle

Self Refresh Exit Time

Refresh Period (4096 cycles)

tSREX

tREF

2Clk

+tRC

–

–

ns 8

64

ms 7

Read Cycle

Data Out Hold Time

tOH

Data Out to Low Impedance Time

tLZ

Data Out to High Impedance Time

tHZ

CAS Latency = 3

CAS Latency = 2

CAS Latency = 1

3

–

ns

0

–

ns

9

–

6

ns

–

8

ns

–

25

ns

DQM Data Out Disable Latency

tDQZ

2

–

CLK

Write Cycle

Data In Setup Time

Data In Hold Time

Data input to Precharge

Data In to Active/refresh

DQM Write Mask Latency

tDS

3

tDH

1

tDPL

2

tDAL

5

tDQW

0

–

ns

–

ns

–

CLK

–

CLK 10

–

CLK

Semiconductor Group

8

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