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IDT72815LB35BG

CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024 x 18

Integrated Device Technology 

IDT72805/72815/72825 CMOS Dual SyncFIFO™

256 x 18, 512 x 18, and 1024 x 18

COMMERCIAL TEMPERATURE RANGE

SIGNAL DESCRIPTIONS:

INPUTS:

DATA IN (DA0 - DA17, DB0 - DB17)

Data inputs for 18-bit wide data.

CONTROLS:

RESET (RSA, RSB)

Reset is accomplished whenever the Reset (RSA, RSB)

input is taken to a LOW state. During reset, both internal read

and write pointers are set to the first location. A reset is

required after power-up before a write operation can take

place. The Full Flag (FFA, FFB), Half-Full Flag (HFA, HFB),

and Programmable Almost-Full Flag (PAFA, PAFB) will be

reset to HIGH after tRSF. The Empty Flag (EFA, EFB) and

Programmable Almost-Empty Flag (PAEA, PAEB) will be

reset to LOW after tRSF. During reset, the output register is

initialized to all zeros and the offset registers are initialized to

their default values.

WRITE CLOCK (WCLKA, WCLKB)

A write cycle is initiated on the LOW-to-HIGH transition of

the write clock (WCLKA, WCLKB). Data set-up and hold times

must be met with respect to the LOW-to-HIGH transition of

WCLK.

The write and read clocks can be asynchronous or

coincident.

WRITE ENABLE (WENA, WENB)

When Write Enable (WENA, WENB) is LOW, data can be

loaded into the input register and RAM array on the LOW-to-

HIGH transition of every WCLK. Data is stored in the RAM

array sequentially and independently of any on-going read

operation.

When WEN is HIGH, the input register holds the previous

data and no new data is loaded into the FIFO.

To prevent data overflow, FF will go LOW, inhibiting further

write operations. Upon the completion of a valid read cycle,

the FF will go HIGH after tWFF allowing a write to begin. WEN

is ignored when the FIFO is full.

READ CLOCK (RCLKA, RCLKB)

Data can be read on the outputs on the LOW-to-HIGH

transition of the read clock (RCLKA, RCLKB), when the

Output Enable (OEA, OEB) is set LOW.

The write and read clocks can be asynchronous or

coincident.

READ ENABLE (RENA, RENB)

When Read Enable (RENA, RENB) is LOW, data is loaded

into the RAM array to the output register on the LOW-to-HIGH

transition of the RCLK.

When REN is HIGH, the output register holds the previous

data and no new data is loaded into the register.

When all the data has been read from the FIFO, EF will go

LOW, inhibiting further read operations. Once a write is

performed, the EF will go HIGH after tREF and a read can

begin. REN is ignored when the FIFO is empty.

OUTPUT ENABLE (OEA, OEB)

When Output Enable (OEA, OEB) is enabled (LOW), the

parallel output buffers receive data from the output register.

When OE is disabled (HIGH), the Q output data bus is in a

high-impedance state.

LOAD (LDA, LDB)

The IDT72805LB/72815LB/72825LB devices contain two

10-bit offset registers with data on the inputs, or read on the

outputs. When the Load (LDA, LDB) pin is set LOW and WEN

is set LOW, data on the inputs D0-D19 is written into the Empty

offset register on the first LOW-to-HIGH transition of WCLK.

When LD and WEN are held LOW then data is written into the

Full offset register on the second LOW-to-HIGH transition of

WCLK. The third transition of WCLK again writes to the Empty

offset register.

However, writing all offset registers does not have to occur

at one time. One or two offset registers can be written and then

by bringing LD HIGH, the FIFO is returned to normal read/

write operation. When LD is set LOW, and WEN is LOW, the

next offset register in sequence is written.

When LD is LOW and WEN is HIGH, the WCLK input is

disabled; then a signal at this input can neither increment the

write offset register pointer, nor execute a write.

The contents of the offset registers can be read on the

output lines when LD is set LOW and REN is set LOW; then,

data can be read on the LOW-to-HIGH transition of RCLK. The

act of reading the control registers employs a dedicated read

offset register pointer. (The read and write pointers operate

independently).

A read and a write should not be performed simultaneously

to the offset registers.

LDA WENA WCLKA(1)

LDB WENB WCLKB(1)

0

0

Selection

Writing to offset registers:

Empty Offset

Full Offset

0

1

No Operation

1

0

Write Into FIFO

1

1

No Operation

NOTE:

3139 tbl 08

1. The same selection sequence applies to reading from the registers. REN

is enabled and read is performed on the LOW-to-HIGH transition of RCLK.

Figure 2. Write Offset Register

5.17

6

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