IDT72815LB35BG 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72815LB35BG

CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024 x 18

Integrated Device Technology 

IDT72805/72815/72825 CMOS Dual SyncFIFO™

256 x 18-BIT, 512 x 18, and 1024 x 18

WCLK

D0 - D17

WEN

RCLK

EF

t DS

D0 (first valid write)

t ENS

tSKEW2

D1

t

(1)

FRL

t REF

COMMERCIAL TEMPERATURE RANGE

D2

D3

D4

REN

Q0 - Q17

OE

tA

t OLZ

t OE

tA

D0

D1

3139 drw 07

NOTES:

1. When tSKEW2 ≥ minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK +

tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).

2. The first word is available the cycle after EF goes HIGH, always.

Figure 7. First Data Word Latency after Reset with Simultaneous Read and Write

5.17

11

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