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IDT72805LB

CMOS DUAL SyncFIFO DUAL 256 x 18 DUAL 512 x 18 DUAL 1,024 x 18 DUAL 4,096 x 18

Integrated Device Technology 

IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFOTM

256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET

FL RXI WXI

EF/OR

FF/IR

PAE, PAF

0

0

0

0

0

1

0(1)

1

1

0

1

0

1

1

1(2)

1

0 Single register-buffered

Empty Flag

1 Triple register-buffered

Output Ready Flag

0 Double register-buffered

Empty Flag

1 Single register-buffered

Empty Flag

0 Single register-buffered

Empty Flag

1 Triple register-buffered

Output Ready Flag

0 Double register-buffered

Empty Flag

1 Single register-buffered

Empty Flag

Single register-buffered

Full Flag

Double register-buffered

Input Ready Flag

Double register-buffered

Full Flag

Single register-buffered

Full Flag

Single register-buffered

Full Flag

Double register-buffered

Input Ready Flag

Double register-buffered

Full Flag

Single register-buffered

Full Flag

Asynchronous

Asynchronous

Asynchronous

Asynchronous

Synchronous

Synchronous

Synchronous

Asynchronous

FIFO TIMING MODE

Standard

FWFT

Standard

Standard

Standard

FWFT

Standard

Standard

NOTES:

1. In a daisy-chain depth expansion, FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.

2. In a daisy-chain depth expansion, FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and

WXO outputs of the preceding device.

TABLE 4 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — IDT STANDARD MODE

Empty Flag (EF)

Buffered Output

Full Flag (FF)

Buffered Output

Partial Flags

Timing Mode

Programming at Reset

FL

RXI

WXI

Flag Timing

Diagrams

Single

Single

Double

Double

Single

Single

Double

Double

Asynch

Sync

Asynch

Synch

0

0

0

1

0

0

0

1

0

1

1

0

Figure 9, 10

Figure 9, 10

Figure 24, 26

Figure 24, 26

TABLE 5 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — FWFT MODE

Output Ready (OR)

Input Ready (IR)

Partial Flags

Programming at Reset

Flag Timing

FL

RXI

WXI

Diagrams

Triple

Triple

Double

Double

Asynch

Sync

0

0

1

1

0

1

Figure 27

Figure 20, 21

9

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