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IDT72805LB 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72805LB Datasheet PDF : 26 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C + 85°C)
Commercial
Com’l & Ind’l(1)
Symbol
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSS
tRSR
tRSF
tOLZ
tOE
tOHZ
tWFF
tREF
tPAFA
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width(2)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z(3)
Output Enable to Output Valid
Output Enable to Output in High-Z(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Asynchronous Programmable
Almost-Full Flag
IDT72805LB10
IDT72815LB10
IDT72825LB10
IDT72845LB10
Min.
Max.
100
2
6.5
10
4.5
4.5
3
0
3
0
10
8
8
15
0
6
1
6
6.5
6.5
17
IDT72805LB15
IDT72815LB15
IDT72825LB15
IDT72845LB15
Min.
Max.
66.7
2
10
15
6
6
4
1
4
1
15
10
10
15
0
8
1
8
10
10
20
tPAFS
Write Clock to Synchronous
Programmable Almost-Full Flag
tPAEA
Clock to Asynchronous Programmable
Almost-Empty Flag
8
10
17
20
tPAES
tHF
tXO
tXI
tXIS
tSKEW1
tSKEW2(4)
Read Clock to Synchronous
Programmable Almost-Empty Flag
Clock to Half-Full flag
Clock to Expansion Out
Expansion In Pulse Width
Expansion In Setup Time
Skew time between Read Clock &
Write Clock for FF/IR and EF/OR
Skew time between Read Clock &
Write Clock for PAE and PAF
8
10
17
20
6.5
10
3
6.5
3
5
5
6
12
15
Commercial
IDT72805LB25
IDT72815LB25
IDT72825LB25
IDT72845LB25
Min.
Max.
40
3
15
25
10
10
6
1
6
1
25
15
15
25
0
12
1
12
15
15
35
12
35
12
35
15
10
10
10
17
NOTES:
1. Industrial Temperature Range Product for the 15ns speed grade is available as a standard device.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. tSKEW2 applies to synchronous PAE and synchronous PAF only.
5V
1.1K
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
D.U.T.
680Ω
30pF*
3139 drw 03
Figure 1. Output Load
* Includes jig and scope capacitances.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6

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