IDT72805LB 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT72805LB
Integrated Device Technology
IDT72805LB Datasheet PDF : 26 Pages
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IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
CONTROLS:
RESET (RSA/RSB)
Reset is accomplished whenever the Reset (RSA/RSB) input is taken to
a LOW state. During reset, both internal read and write pointers are set to
the first location. A reset is required after power-up before a write operation
can take place. The Half-Full flag (HFA/HFB) and Programmable Almost-
Full flag (PAFA/PAFB) will be reset to HIGH after tRSF. The Programmable
Almost-Empty flag (PAEA/PAEB) will be reset to LOW after tRSF. The Full
Flag (FFA/FFB) will reset to HIGH. The Empty Flag (EFA/EFB) will reset to
LOW in IDT Standard mode but will reset to HIGH in FWFT mode. During
reset, the output register is initialized to all zeros and the offset registers are
initialized to their default values.
WRITE CLOCK (WCLKA/WCLKB)
A write cycle is initiated on the LOW-to-HIGH transition of the Write
Clock (WCLKA/WCLKB). Data setup and hold times must be met with
respect to the LOW-to-HIGH transition of WCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (WENA/WENB)
When the WENA/WENB input is LOW, data may be loaded into the FIFO
RAM array on the rising edge of every WCLK cycle if the device is not full.
Data is stored in the RAM array sequentially and independently of any
ongoing read operation.
When WEN is HIGH, no new data is written in the RAM array on each
WCLK cycle.
To prevent data overflow in the IDT Standard Mode, FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF flag is updated on the rising
edge of WCLK.
To prevent data overflow in the FWFT mode, Input Ready (IRA,IRB) will
go HIGH, inhibiting further write operations. Upon the completion of a valid
read cycle, IR will go LOW allowing a write to occur. The IR flag is updated
on the rising edge of WCLK.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode.
READ CLOCK (RCLKA/RCLKB)
Data can be read on the outputs on the LOW-to-HIGH transition of the
Read clock (RCLKA/RCLKB), when Output Enable (OEA/OEB) is set LOW.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (RENA/RENB)
When Read Enable (RENA/RENB) is LOW, data is loaded from the RAM
array into the output register on the rising edge of every RCLK cycle if the
device is not empty.
When the REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EFA/EFB) will go
LOW, inhibiting further read operations. REN is ignored when the FIFO is
LD WEN
0
0
WCLK
Selection
Writing to offset registers:
Empty Offset
Full Offset
0
1
1
0
No Operation
Write Into FIFO
1
1
No Operation
NOTE:
1. The same selection sequence applies to reading from the registers. REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
Figure 2. Writing to Offset Registers
17
11
0
EMPTY OFFSET REGISTER
DEFAULT VALUE
001FH (72805) 003FH (72815):
007FH (72825/72845)
17
1
0
1
FULL OFFSET REGISTER
DEFAULT VALUE
001FH (72805) 003FH (72815):
007FH (72825/72845)
NOTE:
3139 drw 04
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
empty. Once a write is performed, EF will go HIGH allowing a read to occur.
The EF flag is updated on the rising edge of RCLK.
In the FWFT mode, the first word written to an empty FIFO automatically
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK
+ tSKEW after the first write. REN does not need to be asserted LOW. In order
to access all other words, a read must be executed using REN. The RCLK
LOW to HIGH transition after the last word has been read from the FIFO,
Output Ready (ORA/ORB) will go HIGH with a true read (RCLK with REN
= LOW), inhibiting further read operations. REN is ignored when the FIFO
is empty.
OUTPUT ENABLE (OEA/OEB)
When Output Enable (OEA/OEB) is enabled (LOW), the parallel output
buffers receive data from the output register. When OE is disabled (HIGH),
the Q output data bus is in a high-impedance state.
LOAD (LDA/LDB)
The IDT72805LB/72815LB/72825LB/72845LB devices contain two 12-bit
offset registers with data on the inputs, or read on the outputs. When the Load
(LDA/LDB) pin is set LOW and WEN is set LOW, data on the inputs D0-D11 is
written into the Empty Offset register on the first LOW-to-HIGH transition of the
Write clock (WCLK). When the LD pin and WEN are held LOW then data is written
into the Full Offset register on the second LOW-to-HIGH transition of WCLK. The
third transition of WCLK again writes to the Empty Offset register.
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing the LD pin HIGH, the
FIFO is returned to normal read/write operation. When the LD pin is set LOW,
and WEN is LOW, the next offset register in sequence is written.
10
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