IDT72801(2001) 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT72801 Datasheet PDF : 16 Pages
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IDT72801/728211/72821/72831/72841/72851
Commercial And Industrial Temperature Range
TWO PRIORITY DATA BU..ER
CON.IGURATION
The two FIFOs contained in the IDT72801/72811/72821/72831/72841/
72851 can be used to prioritize two different types of data shared on a system
bus. When writing from the bus to the FIFO, control logic sorts the intermixed
data according to type, sending one kind to FIFO A and the other kind to FIFO
B. Then, at the outputs, each data type is transferred to its appropriate
destination. Additional IDT72801/72811/72821/72831/72841/72851s permit
more than two priority levels. Priority buffering is particularly useful in network
applications.
Processor
Clock
Address
Control
Data
RAM
RAM ARRAY A
RCLKA
Image Processing
Card
Clock
WCLKA OEA
WENA1 RENA
9
DA0-DA8
9
QA0-QA8
VCC
WENA2 RENA2
Data
Address
Control
IDT
72801
72811
72821
72831
72841
72851
Voice Processing
Card
9
RAM ARRAY B
WCLKB RCLKB
Clock
WENB1 OEB2
9
RENB1
Address
Control
DB0-DB8 QB0-QB8
Data
9
WENB2 RENB2
9
VCC
Figure 16. Block Diagram of Two Priority Configuration
I/O Data
I/O Data
3034 drw 17
BIDIRECTIONAL CON.IGURATION
The two FIFOs of the IDT72801/72811/72821/72831/72841/72851 can
be used to buffer data flow in two directions. In the example that follows, a
processor can write data to a peripheral controller via FIFO A, and, in turn,
the peripheral controller can write the processor via FIFO B.
Processor
Clock
Address
Control
Data
9
RAM
9
RAM ARRAY A
VCC
WENA2 RENA2
RCLKA
WCLKA OEA
WENA1
RENA1
9
DA0-DA8
QA0-QA8
9
IDT
72801
72811
72821
72831
72841
72851
RAM ARRAY B
RCLKB WENB1
RENB1
OEB WCLKB
QB0-QB8
9
DB0-DB8
RENB2 WENB2
9
Peripheral
Controller
DMA Clock
Address
Control
Data
9
I/O Data
3034 drw 18
Figure 17. Block Diagram of Bidirectional Configuration
15
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