IDT72801(2001) 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT72801 Datasheet PDF : 16 Pages
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IDT72801/728211/72821/72831/72841/72851
Commercial And Industrial Temperature Range
OPERATING CON.IGURATIONS
can be grounded (see Figure 14). In this configuration, the Write Enable 2/
SINGLE DEVICE CONFIGURATION — When FIFO A (B) is in a Single Load WENA2/LDA (WENB2/LDB) pin is set LOW at Reset so that the pin
Device Configuration, the Read Enable 2 RENA2 (RENB2) control input operates as a control to load and read the programmable flag offsets.
RSA (RSB)
WCLKA (WCLKB)
WENA1 (WENB1)
WENA2/LDA (WENB2/LDB)
DA0 - DA8 (DB0 - DB8)
FFA (FFB)
PAFA (PAFB)
IDT
72801
72811
72821
72831
72841
72851
FIFO
A (B)
RCLKA (RCLKB)
RENA1 (RENB1)
OEA (OEB)
QA0 - QA8 (QB0 - QB8)
EFA (EFB)
PAEA (PAEB)
RENA2 (RENB2)
Figure 14. Block Diagram of One of the IDT72801/72811/72821/72831/72841/72851's two FIFOs
configured as a single device
3034 drw 15
WIDTH EXPANSION CONFIGURATION — Word width may be in-
creased simply by connecting the corresponding input control signals of
FIFOs A and B. A composite flag should be created for each of the endpoint
status flags EFA and EFB, also FFA and FFB). The partial status flags
PAEA, PAFB, PAEA and PAFB can be detected from any one device.
Figure 15 demonstrates an 18-bit word width using the two FIFOs contained
in one IDT72801/72811/72821/72831/72841/72851. Any word width can
be attained by adding additional IDT72801/72811/72821/72831/72841/
72851s.
When these devices are in a Width Expansion Configuration, the Read
Enable 2 (RENA2 and RENB2) control inputs can be grounded (see
Figure 15). In this configuration, the Write Enable 2/Load (WENA2/LDA,
WENB2/LDB) pins are set LOW at Reset so that the pin operates as a
control to load and read the programmable flag offsets.
9
RESET
RSA DB0 - DB8
RSB
EFA
DATA IN
18
9 DA0 - DA8
RAM
RAM
EFB
ARRAY RCLKA
ARRAY RCLKB
WRITE CLOCK
WCLKA
A
WCLKB B
256x9 RENA1
256x9 RENB1
WRITE ENABLE
WENA1
512x9
WENB1 512x9
1,024x9 OEA1
1,024x9 OEB
WRITE ENABLE/LOAD
WENA2/LDA 2,048x9 2WENB2/LDB 2,048x9
4,096x9
4,096x9
FULL FLAG
FFA
8,192x9
FFB
8,192x9 QB0 - QB8
9
RENA2
QA0 - QA8 RENB2
EMPTY FLAG
READ CLOCK
READ ENABLE
OUTPUT ENABLE
18 DATA OUT
9
Figure 15. Block diagram of the two FIFOs contained in one IDT72801/72811/
72821/72831/72841/72851 configured for an 18-bit width-expansion
14
3034 drw 16
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