IDT72205LB10TF(2000) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72205LB10TF
(Rev.:2000)

CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

Integrated Device Technology 

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™

256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

WCLK

tDS

D0 - D17

tENS

DATA WRITE 1

tENH

RCLK

tSKEW2

tFRL (1)

tREF

tDS

tENS

tREF

Commercial And Industrial Temperature Ranges

DATA WRITE 2

tENH

tSKEW2

tFRL (1)

tREF

LOW

tA

Q0 - Q17

DATA IN OUTPUT REGISTER

DATA READ

NOTE:

2766 drw 11

1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW2,

or tCLK + tSKEW2. The Latency Timing apply only at the Empty Boundary (EF = LOW).

Figure 9. Empty Flag Timing

WCLK

LD

WEN

D0–D15

tCLK

tCLKH

tCLKL

tENS

tENS

tDS

PAE OFFSET

tENH

tDH

PAE OFFSET

PAF OFFSET

D0–D11

Figure 10. Write Programmable Registers

2766 drw 12

tCLKH

RCLK

tCLK

tCLKL

tENS

tENH

tENS

Q0–Q15

tA

UNKNOWN

PAE OFFSET

PAF OFFSET

Figure 11. Read Programmable Registers

PAE OFFSET

2766 drw 13

11

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