IDT72205LB10TF(2000) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72205LB10TF
(Rev.:2000)

CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

Integrated Device Technology 

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™

256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

DEPTH EXPANSION CONFIGURATION

(WITH PROGRAMMABLE FLAGS)

These devices can easily be adapted to applications requir-

ing more than 256/512/1,024/2,048/4,096 words of buffering.

Figure 21 shows Depth Expansion using three IDT72205LB/

72215LB/72225LB/72235LB/72245LBs. Maximum depth is

limited only by signal loading. Follow these steps:

1. The first device must be designated by grounding the

First Load (FL) control input.

2. All other devices must have FL in the HIGH state.

3. The Write Expansion Out (WXO) pin of each device

must be tied to the Write Expansion In (WXI) pin of

Commercial And Industrial Temperature Ranges

the next device. See Figure 21.

4. The Read Expansion Out (RXO) pin of each device

must be tied to the Read Expansion In (RXI) pin of

the next device. See Figure 21.

5. All Load (LD) pins are tied together.

6. The Half-Full Flag (HF) is not available in this Depth

Expansion Configuration.

7. EF, FF, PAE, and PAF are created with composite

flags by ORing together every respective flags for

monitoring. The composite PAE and PAF flags are not

precise.

WCLK

RCLK

IDT

72205LB

72215LB

Dn 72225LB Qn

Vcc

72235LB

72245LB

DATA IN

WCLK

RCLK

Vcc

IDT

72205LB

72215LB

Dn 72225LB Qn

72235LB

72245LB

DATA OUT

WRITE CLOCK

WRITE ENABLE

RESET

LOAD

WCLK RCLK

Dn

IDT Qn

72205LB

72215LB

72225LB

72235LB

72245LB

READ CLOCK

READ ENABLE

OUTPUT ENABLE

FIRST LOAD ( )

Figure 21. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous

FIFO Memory With Programmable Flags used in Depth Expansion Configuration

2766 drw 23

15

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