ICS9250-29 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS9250-29

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Integrated Circuit Systems 

ICS9250-29

Truth Table

Tristate FS0 FS1 CPU

0

0 X Tristate

0

1 X TCLK/2

1

0 0 66.6 MHz

1

1 0 100 MHz

1

0 1 133 MHz

1

1 1 133 MHz

SDRAM 3V66

PCI

Tristate Tristate Tristate

TCLK/2 TCLK/3 TCLK/6

100 MHz 66.6 MHz 33.3 MHz

100 MHz 66.6 MHz 33.3 MHz

133 MHz 66.6 MHz 33.3 MHz

100 MHz 66.6 MHz 33.3 MHz

48MHz

Tristate

TCLK/2

48 MHz

48 MHz

48 MHz

48 MHz

REF

IOAPIC

Tristate

Tristate

TCLK

TCLK/6

14.318 MHz 33.3 MHz

14.318 MHz 33.3 MHz

14.318 MHz 33.3 MHz

14.318 MHz 33.3 MHz

Byte 0: Control Register

(1 = enable, 0 = disable)

Bit Pin#

Name

PWD Description

Bit 7 - (Reserved ID)

0 (Active / Inactive )

Bit 6 - (Reserved ID)

0 (Active / Inactive )

Bit 5 - (Reserved ID)

0 (Active / Inactive )

Bit 4 - (Reserved ID)

1 (Active / Inactive )

Bit 3 - Spread Spectrum 0 (1=On / 0=Off )

Bit 2 29 48MHz_1

1 (Active / Inactive )

Bit 1 28 48MHz_0

1 (Active / Inactive )

Bit 0 - (Reserved ID)

0 (Active / Inactive )

Note:

Reserved ID bits must be written with "0"

Byte 1: Control Register

(1 = enable, 0 = disable)

Bit Pin#

Name

Bit 7 40 SDRAM7

Bit 6 41 SDRAM6

Bit 5 44 SDRAM5

Bit 4 45 SDRAM4

Bit 3 46 SDRAM3

Bit 2 47 SDRAM2

Bit 1 50 SDRAM1

Bit 0 51 SDRAM0

PWD Description

1 (Active / Inactive )

1 (Active / Inactive )

1 (Active / Inactive )

1 (Active / Inactive )

1 (Active / Inactive )

1 (Active / Inactive )

1 (Active / Inactive )

1 (Active / Inactive )

5

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