ICS9250-29 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS9250-29 Datasheet PDF : 15 Pages
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ICS9250-29
General Description
The ICS9250-29 is a single chip clock solution for Solano type chipset. It provides all necessary clock signals for such
a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-29
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Pin Configuration
PIN NUMBER PIN NAME
1
IOAPIC
2, 55
VDDL
3, 56
GNDL
4
5, 9, 17, 23, 27,
33, 37, 43, 49
FS1
REF
VDDx
6
X1
7
X2
8, 13, 18, 22, 26,
32, 36, 42, 48, 52
GNDx
12, 11, 10 3V66 (2:0)
21
FS0
20, 19, 16, 15, 14 PCICLK (4:0)
TRISTATE#
30
PD#
24
SCLK
TYPE
DESCRIPTION
OUT 2.5V clock output running at 33.3MHz.
PWR 2.5V power supply for CPU & IOAPIC
PWR Ground for 2.5V power supply for CPU & IOAPIC
IN Function Select pin. Determines CPU frequency, all output functionality
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply
IN
OUT
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
PWR Ground pins for 3.3V supply
OUT 3.3V Fixed 66MHz clock outputs for HUB
IN Function Select pin. Determines CPU frequency, all output functionality.
OUT 3.3V PCI clock outputs
At power up the TRISTATE#/PD# pin defaults to the TRISTATE#
IN input function to enable the TRISTATE# and TEST modes. (see Shared
Pin Operation for full description).
Asynchronous active low input pin used to power down the device into
IN
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
IN Clock input of I2C input
25
SDATA
IN Data input for I2C serial input.
29, 28
48MHz (1:0)
31, 34, 35, 38,
39, 40, 41, 44,
45, 46, 47, 50, 51
SDRAM
[12:0]
53, 54
CPUCLK (1:0)
OUT 3.3V Fixed 48MHz clock outputs.
OUT
3.3V output running 100MHz and 133MHz. All SDRAM outputs can
be turned off through I2C
OUT
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS pins.
2
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