ICS9250-13 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS9250-13

Frequency Generator & Integrated Buffers for PENTIUM/Pro™

Integrated Circuit Systems 

ICS9250 - 13

CPU_STOP# Timing Diagram

CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.

CPU_STOP# is synchronized by the ICS9250-13. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100

CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in

a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4

CPU clocks and CPU clock off latency is less than 4 CPU clocks.

Notes:

1. All timing is referenced to the internal CPU clock.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized

to the CPU clocks inside the ICS9250-13.

3. All other clocks continue to run undisturbed. (including SDRAM outputs).

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