ICS9250-13 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS9250-13 Datasheet PDF : 15 Pages
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ICS9250 - 13
Pin Descriptions
PIN NUMBER
PIN NAME
1
VDDREF
REF0
2
FS31, 2
3,9,16,22,28, 29, 35,
41, 47, 53
GND
4
X1
5
X2
6,14
7
8
10, 11, 12, 13
15
VDDPCI
PCICLK_F
FS11, 2
PCICLK0
FS21, 2
PCICLK(1:4)
PCICLK5
PCI_STOP#1
17, 18, 20, 21, 26,
27, 30, 31, 36, 37,
39, 40, 42, 43, 45,
46
SDRAM (0:15)
19, 25, 38, 44 VDDSDR
23
SDATA
24
SCLK
32
VDD48
24MHz
33
MODE1, 2
34
48, 49, 51, 52
50
48MHz
FS01, 2
CPUCLK(0:3)
VDDLCPU
REF1
54
CPU_STOP#1
55
IOAPIC
56
VDDLIOAPIC
TYPE
PWR
OUT
IN
DESCRIPTION
Ref (0:1), XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
Frequency select pin. Latched Input
PWR Ground
IN
OUT
PWR
OUT
IN
OUT
IN
OUT
OUT
IN
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock
Frequency select pin. Latched Input
PCI clock output.
Frequency select pin. Latched Input
PCI clock outputs.
PCI clock output. (In desktop mode, MODE=1)
Halts PCICLK(0:5) clocks at logic 0 level, when input low
(In mobile mode, MODE=0)
OUT SDRAM clock outputs.
PWR
IN
IN
PWR
OUT
IN
OUT
IN
OUT
PWR
OUT
IN
OUT
PWR
Supply for SDRAM (0:15), PLL Core and 24MHz clocks,
nominal 3.3V.
Data input for I2C serial input.
Clock input of I2C input
Supply for 48MHz clocks 3.3V nominal
24MHz output clock
Pin 15, pin 54 function select pin, 1=Desktop Mode,
0=Mobile Mode. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Supply for CPU (0:3), either 2.5V or 3.3V nominal
14.318 MHz reference clock, (in Desktop Mode, MODE=1) This REF output
is the STRONGER buffer for ISA BUS loads.
Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile
Mode, MODE=0)
IOAPIC clock output. 14.318 MHz Powered by VDDL1.
Supply for IOAPIC, either 2.5 or 3.3V nominal
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2
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