HEF4534B 데이터 시트보기 (PDF) - Philips Electronics

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HEF4534B

LSI Real time 5-decade counter

Philips Electronics 

Philips Semiconductors

Real time 5-decade counter

Product specification

HEF4534B

LSI

MODE CONTROL FUNCTION TABLE

SELECT INPUTS 1ST DECADE

SA

SB

OUTPUT

normal count

L

L

and display

L

H inhibited

H

H inhibited

display counts:

H

L 3, 4, 5, 6, 7 = 5

8, 9, 0, 1, 2 = 0

CARRY TO 2ND STAGE CARRY TO 4TH STAGE

MODE

at 9 to 0 transition

of the 1st decade

input clock

at 4 to 5 transition

of the 1st decade

at 7 to 8 transition

of the 1st decade

at 9 to 0 transition

of the 3rd decade

input clock

at 9 to 0 transition

of the 3rd decade

at 9 to 0 transition

of the 3rd decade

5-decade

counter

test purposes:

clock directly into

stages 1, 2 and 4

4-decade counter

with ÷ 10 and round-

off at front end

4-decade counter;

1⁄2-pence capability

Fig.3 Error detection timing diagram.

The skew time is the time difference between the LOW to

HIGH transition of CPA and the HIGH to LOW transition of

CPE or vice versa (see Fig.4). The skew time is typically

proportional to the external capacitor (Cext) connected

from Cext1 and Cext2 (pins 1 and 22) to VSS. The error

detector will count an error when a positive edge on the

counter clock CPA is not succeeded by a negative edge on

the error detector clock CPE within a skew time

tSK1 (adjustable by Cext1 at pin 1). The same holds for a

negative edge at CPE succeeded by a positive on CPA

within a skew time tSK2 (adjustable by Cext2 at pin 22). If

error detection is not needed, CPE must be either HIGH or

LOW and no Cext is applied. For further information see

Fig.5.

Fig.4

Skew times

timing diagram;

tWCPA > tSK1;

tWCPE > tSK2.

January 1995

4

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