AN-6921 데이터 시트보기 (PDF) - Fairchild Semiconductor
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AN-6921
Fairchild Semiconductor
AN-6921 Datasheet PDF : 16 Pages
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AN-6921
N min
P
=
Lm IDS PK
AeΔB
=
700 ×10−6
159 ×10−6
⋅
⋅
2.28
0.26
= 38.6
NP
=
n⋅ NS
=
6.84 ⋅ 5
=
34
<
N min
P
=
n⋅ NS
=
6.84⋅ 6
=
41 >
N min
P
N AUX
=
V nom
DD
+ VFA
(VO + VF )
⋅ NS
= 18 +1.2 ⋅ 6 = 6
19
Assuming the pulse-by-pulse current limit for low
PFC output voltage is 125% of peak drain current at
heavy load:
Bmax
=
Lm I LIM
Ae NP
= 700 ⋅ 2.28 ⋅1.25 = 0.31T
159 ⋅ 41
VO
⋅
NA
NS
−PFC
_
VO
⋅
NA
NP
VO
⋅
NA
NS
⋅
RA
RDET +
RA
APPLICATION NOTE
[STEP-B3] Design the Valley Detection Circuit
The valley of MOSFET voltage is detected by monitoring
the current flowing out of DET pin. The typical application
circuit is shown as Figure 13 and typical waveforms are
shown in Figure 14. The DET pin has upper and lower
voltage clamping at 5V and 0.7V, respectively. The valley
detection circuit is blanked for 8µs after the MOSFET is
turned off. When VAUX drops below zero, VDET is clamped at
0.7V and current flows out of the DET pin. MOSFET is
turned on with 200ns time delay once the current flowing
out of DET pin exceeds 30µA. To guarantee that valley
detection circuit is triggered when DET pin is clamped at
0.7V, the current flowing through RDET2 should be larger
than 30µA as:
0.7 > 30μ A
RDET 2
(32)
Figure 13. Typical Application Circuit of DET Pin
Figure 14. Waveforms of Valley Detection and
VO OVP Detection
The output voltage is indirectly monitored for over-voltage
protection using the DET pin voltage while the MOSFET is
turned off. Thus, the ratio of RDET1 and RDET2 should be
determined as:
2.5 =
RDET 2
RDET1 + RDET 2
N
N
A
S
VOVP
=
1
K DET
+
1
NA
NS
VOVP
(33)
where the ratio between RDET1 and RDET2 is obtained as:
KDET
=
RDET 1
RDET 2
=
NA
NS
⋅ VOVP
2. 5
−1
(34)
For a quasi-resonant flyback converter, the peak drain
current with a given output power decreases as input voltage
increases. Thus, constant power limit cannot be achieved by
just using pulse-by-pulse current limit with constant
threshold. FAN6921 has high/low line over power
compensation that reduces the pulse-by-pulse current limit
level as input voltage increases. FAN6921 senses the input
voltage using the current flowing out of the DET pin while
the MOSFET is turned on. The pulse-by-pulse current limit
level vs. DET current is depicted in Figure 16.
The DET pin current for low line and high line PFC output
voltages are given as:
I DET .L
=
VO.PFC.L
NA
NP
+0.7
RDET 1
+
0. 7
RDET 2
VO.PFC.L
≅
NA
NP
RDET 1
(35)
I DET .H
VO.PFC.H
=
NA +0.7
NP
+
RDET 1
0. 7
RDET 2
VO.PFC.H
≅
NA
NP
RDET 1
(36)
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 8/24/10
10
www.fairchildsemi.com
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