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CY7C43662-10AC Datasheet PDF : 30 Pages
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CY7C43642
CY7C43662
CY7C43682
words in memory to [1024/4096/16384–(Y+1)]. An Almost Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizing clock after the FIFO read that reduces the
number of words in memory to [1024/4096/16384–(Y+1)]. A
LOW-to-HIGH transition of an Almost Full flag synchronizing
clock begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of
words in memory to [1024/4096/16384–(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first
synchronization cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A0-35 data to the
Mail1 Register when a Port A write is selected by CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register
employs data lines A0-35. If the selected Port A bus size is 18
bits, then the usable width of the Mail1 Register employs data
lines A0-17. (In this case, A18-35 are don’t care inputs.) If the
selected Port A bus size is 9 bits, then the usable width of the
Mail1 Register employs data lines A0-8. (In this case, A9-35 are
don’t care inputs.)
A LOW-to-HIGH transition on CLKB writes B0–35 data to the
Mail2 Register when a Port B write is selected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register
employs data lines B0–35. If the selected Port B bus size is 18
bits, then the usable width of the Mail2 Register employs data
lines B0–17. (In this case, B18–35 are don’t care inputs.) If the
selected Port B bus size is 9 bits, then the usable width of the
Mail2 Register employs data lines B0-8. (In this case, B9-35 are
don’t care inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while the mail flag is LOW.
Table 1. Flag Programming[2]
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B read is
selected by CSB, W/RB, and ENB with MBB HIGH. For a
36-bit bus size, 36 bits of mailbox data are placed on B0–35.
For an 18-bit bus size, 18 bits of mailbox data are placed on
B0–17. (In this case, B18–35 are indeterminate.) For a 9-bit bus
size, 9 bits of mailbox data are placed on B0–8. (In this case,
B9–35 are indeterminate.)
The Mail2 Register flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A read is
selected by CSA, W/RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A0–35. For an 18-bit bus size, 18 bits of mailbox data are
placed on A0–17. (In this case, A18–35 are indeterminate.) For
a 9-bit bus size, 9 bits of mailbox data are placed on A0–8. (In
this case, A9–35 are indeterminate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit
function applies to CY standard mode only.
The number of 36-/18-/9-bit words written into the FIFO should
be less than full depth minus 2/4/8 words between the reset of
the FIFO (master or partial) and Retransmit setup.A LOW
pulse on RT1, (RT2) resets the internal read pointer to the first
physical location of the FIFO. CLKA and CLKB may be free
running but ENB (ENA) must be deasserted during and tRTR
after the retransmit pulse. With every valid read cycle after
retransmit, previously accessed data is read and the read
pointer is incremented until it is equal to the write pointer. Flags
are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data
written to the FIFO after activation of RT1, (RT2) are trans-
mitted also.
FS1
FS0
RST1
RST2
X1 and Y1 Registers[3]
X2 and Y2 Registers[4]
H
H
↑
X
64
X
H
H
X
↑
X
64
H
L
↑
X
16
X
H
L
X
↑
X
16
L
H
↑
X
8
X
L
H
X
↑
X
8
L
L
↑
↑
Programming via Port A
Programming via Port A
Table 2. Port A Enable Function
CSA
H
L
W/RA
X
H
ENA
X
L
MBA
X
X
CLKA
X
X
A0–35 Outputs
In high-impedance state
In high-impedance state
None
None
Port Function
Document #: 38-06019 Rev. *B
Page 8 of 30
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