CY7C43662-10AC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C43662-10AC Datasheet PDF : 30 Pages
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AC Test Loads and Waveforms (-10 and -15)
5V
OUTPUT
R1 = 1.1kΩ
CL = 30 pF
R2 = 680Ω
INCLUDING
JIG AND
SCOPE
AC Test Loads and Waveforms (-7)
VCC/2
50 Ω
I/O
Z0 = 50Ω
CY7C43642
CY7C43662
CY7C43682
3.0V
GND
≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤ 3 ns
3.0V
GND
≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤ 3 ns
Switching Characteristics Over the Operating Range
CY7C43642/62/82 CY7C43642/62/82 CY7C43642/62/82
-7
-10
-15
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
fS
Clock Frequency, CLKA or CLKB
133
100
tCLK
Clock Cycle Time, CLKA or CLKB
7.5
10
15
tCLKH
Pulse Duration, CLKA or CLKB HIGH
3.5
4
6
tCLKL
Pulse Duration, CLKA or CLKB LOW
3.5
4
6
tDS
Set-up Time, A0–35 before CLKA↑ and B0–35
3
4
5
before CLKB↑
67 MHz
ns
ns
ns
ns
tENS
Set-up Time, CSA, W/RA, ENA, and MBA before 3
4
CLKA↑; CSB, W/RB, ENB, and MBB before
CLKB↑
5
ns
tRSTS
Set-up Time, RST1, RST2, RT1 or RT2 LOW
before CLKA↑ or CLKB↑[17]
2.5
4
5
ns
tFSS
Set-up Time, FS0 and FS1 before RST1 and
6
RST2 HIGH
7
7.5
ns
tSDS
Set-up Time, FS0 before CLKA↑
3
4
tSENS
Set-up Time, FS1 before CLKA↑
3
4
tFWS
Set-up Time, FWFT before CLKA↑
0
0
tDH
Hold Time, A0–35 after CLKA↑ and B0–35 after
0
0
CLKB↑
5
ns
5
ns
0
ns
0
ns
tENH
Hold Time, CSA, W/RA, ENA, and MBA after
0
0
CLKA↑; CSB, W/RB, ENB, and MBB after
CLKB↑
0
ns
tRSTH
Hold Time, RST1, RST2, RT1 or RT2 LOW after 1
CLKA↑ or CLKB↑[17]
2
4
ns
tFSH
Hold Time, FS0 and FS1 after RST1 and RST2 1
1
HIGH
2
ns
tSDH
Hold Time, FS0 after CLKA↑
0
0
0
ns
tSENH
Hold Time, FS1 after CLKA↑
0
0
0
ns
Note:
17. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
Document #: 38-06019 Rev. *B
Page 11 of 30
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