CY7C43662-10AC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C43662-10AC Datasheet PDF : 30 Pages
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CY7C43642
CY7C43662
CY7C43682
Pin Definitions
Signal Name Description I/O
Function
A0–35
AEA
Port A Data
Port A Almost
Empty Flag
I/O 36-bit bidirectional data port for side A.
O Programmable Almost Empty flag synchronized to CLKA. It is LOW when the number
of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register,
X2.[2]
AEB
Port B Almost
Empty Flag
O Programmable Almost Empty flag synchronized to CLKB. It is LOW when the number
of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register,
X1.[2]
AFA
Port A Almost O Programmable Almost Full flag synchronized to CLKA. It is LOW when the number
Full Flag
of empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1.[2]
AFB
Port B Almost O Programmable Almost Full flag synchronized to CLKB. It is LOW when the number
Full Flag
of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.[2]
B0–35
Port B Data
I/O 36-bit bidirectional data port for side B.
FWFT/STAN Big
I During Master Reset. A HIGH on FWFT selects CY Standard mode, a LOW selects
Endian/First-Wor
First-Word Fall-Through mode. Once the timing mode has been selected, the level on
d Fall-Through
FWFT/STAN must be static throughout device operation.
Select
CLKA
Port A Clock
I CLKA is a continuous clock that synchronizes all data transfers through Port A and
can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all
synchronized to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I CLKB is a continuous clock that synchronizes all data transfers through Port B and
can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all
synchronized to the LOW-to-HIGH transition of CLKB.
CSA
CSB
EFA/ORA
Port A Chip
Select
Port B Chip
Select
Port A Empty/
Output Ready
Flag
I CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HIGH.
I CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B0–35 outputs are in the high-impedance state when CSB is HIGH.
O This is a dual-function pin. In the CY Standard Mode, the EFA function is selected. EFA
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function
is selected. ORA indicates the presence of valid data on
reading. EFA/ORA is synchronized to the LOW-to-HIGH
tAra0–n3s5itioountpouf tCs,LaKvAa.i[l1a]ble
for
EFB/ORB
Port B Empty/
Output Ready
Flag
O This is a dual-function pin. In the CY Standard Mode, the EFB function is selected. EFB
indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function
is selected. ORB indicates the presence of valid data on
reading. EFB/ORB is synchronized to the LOW-to-HIGH
tBra0–n3s5itioountpouftCs,LaKvBa.i[l1a]ble
for
ENA
Port A Enable
I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data
on Port A.
ENB
Port B Enable
I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data
on Port B.
FFA/IRA
Port A Full/Input
Ready Flag
O This is a dual-function pin. In the CY Standard Mode, the FFA function is selected. FFA
indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is
selected. IRA indicates whether or not there is space available for writing to the FIFO1
memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
FFB/IRB
Port B Full/Input
Ready Flag
O This is a dual-function pin. In the CY Standard Mode, the FFB function is selected. FFB
indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is
selected. IRB indicates whether or not there is space available for writing to the FIFO2
memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
Document #: 38-06019 Rev. *B
Page 4 of 30
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