CY7C4265-10ASC(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C4265-10ASC Datasheet PDF : 22 Pages
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Switching Waveforms
Write Cycle Timing
WCLK
tCLKH
tCLK
D0 –D17
WEN
FF
RCLK
tWFF
tSKEW1 [15]
tCLKL
tDS
tENS
CY7C4255
CY7C4265
tDH
tENH
tWFF
NO OPERATION
REN
Read Cycle Timing
RCLK
REN
tENS
EF
Q0 –Q17
OE
WCLK
tOLZ
tCLKH
tCLK
tCLKL
tENH
tREF
tA
NO OPERATION
tOE
tSKEW2[16]
tREF
VALID DATA
tOHZ
4255–6
WEN
4255–7
Notes:
15. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
16. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
Document #: 38-06004 Rev. *B
Page 7 of 22
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