CY7C4225-10AXI 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C4225-10AXI Datasheet PDF : 25 Pages
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CY7C4205/CY7C4215
CY7C4225/CY7C4245
Selection Guide
Description
Maximum frequency (MHz)
Maximum access time (ns)
Minimum cycle time (ns)
Minimum data or enable set-up (ns)
Minimum data or enable hold (ns)
Maximum flag delay (ns)
Operating current (ICC2) (mA) @ 20MHz
Parameter
Density
Packages
CY7C4205
256 x 18
64-pin TQFP
(14 x 14, 10 x 10)
Commercial
Industrial
CY7C4215
512 x 18
64-pin TQFP
(14 x 14, 10 x 10)
-10
100
8
10
3
0.5
8
45
50
CY7C4225
1K x 18
64-pin TQFP
(14 x 14, 10 x 10)
-15
66.7
10
15
4
1
10
45
50
CY7C4245
4K x 18
64-pin TQFP
(14 x 14, 10 x 10)
Pin Definitions
Signal Name Description
D017
Q017
WEN
Data inputs
Data outputs
Write enable
REN
Read enable
WCLK
Write clock
RCLK
Read clock
WXO/HF
EF
FF
PAE
PAF
LD
FL/RT
Write expansion
out/half full flag
Empty flag
Full flag
Programmable
almost empty
Programmable
almost full
Load
First load/
retransmit
WXI
Write expansion
input
RXI
Read expansion
input
IO
Function
I Data inputs for an 18-bit bus.
O Data outputs for an 18-bit bus.
I Enables the WCLK input.
I Enables the RCLK input.
I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
O Dual-mode pin. Single device or width expansion - Half Full status flag. Cascaded – Write
Expansion Out signal, connected to WXI of next device.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied to VCC;
it is synchronized to RCLK when VCC/SMODE is tied to VSS.
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to VCC;
it is synchronized to WCLK when VCC/SMODE is tied to VSS.
I Wmahbelne-LfDlagis-oLffOseWt,rDeg0is1t7er(.O017) are written (read) into (from) the program-
I Dual-mode pin. Cascaded – The first device in the daisy chain will have FL tied to VSS;
all other devices will have FL tied to VCC. In standard mode of width expansion, FL
is tied to VSS on all devices. Not Cascaded – Tied to VSS. Retransmit function is also
available in standalone mode by strobing RT.
I Cascaded – Connected to WXO of previous device. Not cascaded – Tied to VSS.
I Cascaded – Connected to RXO of previous device. Not cascaded – Tied to VSS.
Document Number: 001-45652 Rev. *B
Page 5 of 25
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