CY7C4225-10AXI 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C4225-10AXI Datasheet PDF : 25 Pages
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CY7C4205/CY7C4215
CY7C4225/CY7C4245
Figure 4. AC Test Loads and Waveforms[12, 13]
5V
OUTPUT
R1 = 1.1 K
CL
INCLUDING
JIG AND
SCOPE
R2 =680
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
Rth = 410
Vth = 1.91 V
Switching Characteristics Over the Operating Range
Parameter
tS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSR
tRSF
tPRT
tRTR
tOLZ
tOE
tOHZ
tWFF
tREF
tPAFasynch
tPAFsynch
tPAEasynch
tPAEsynch
Description
Clock cycle frequency
Data access time
Clock cycle time
Clock HIGH time
Clock LOW time.
Data set-up time
Data hold time
Enable set-up time
Enable hold time
Reset pulse width[14]
Reset recovery time
Reset to flag and output time
Retransmit pulse width
Retransmit recovery time
Output enable to output in low Z[15]
Output enable to output valid
Output enable to output in high Z[15]
Write clock to full flag
Read clock to empty flag
Clock to programmable almost-full flag[16]
(Asynchronous mode, VCC/SMODE tied to VCC)
Clock to programmable almost-full flag
(Synchronous mode, VCC/SMODE tied to VSS)
Clock to programmable almost-empty flag[16]
(Asynchronous mode, VCC/SMODE tied to VCC)
Clock to programmable almost-full flag
(Synchronous mode, VCC/SMODE tied to VSS)
3.0 V
GND
3 ns
ALL INPUT PULSES
90%
10%
90%
10%
3 ns
-10
Min
Max
100
2
8
10
4.5
4.5
3
0.5
3
0.5
10
8
10
12
12
0
3
7
3
7
8
8
12
8
12
8
-15
Min
Max
66.7
2
10
15
6
6
4
1
4
1
15
10
15
15
15
0
3
8
3
8
10
10
16
10
16
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12. CL = 30 pF for all AC parameters except for tOHZ.
13. CL = 5 pF for tOHZ.
14. Pulse widths less than minimum values are not allowed.
15. Values guaranteed by design, not currently tested.
16. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
Document Number: 001-45652 Rev. *B
Page 11 of 25
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