CY7C130 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C130

1K x 8 Dual-Port Static RAM

Cypress Semiconductor 

CY7C130/CY7C131

CY7C140/CY7C141

Switching Waveforms (continued)

Write Cycle No. 1 (OE Three-States Data I/Os—Either Port[15, 22]

ADDRESS

CE

R/W

DATAIN

Either Port

tWC

tSCE

tAW

tSA

tPWE

tSD

DATA VALID

tHA

tHD

OE

DOUT

tHZOE

HIGH IMPEDANCE

Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[16, 23]

ADDRESS

CE

R/W

DATAIN

DATAOUT

tWC

tSCE

tHA

tAW

tSA

tPWE

tHZWE

tSD

tHD

DATA VALID

tLZWE

HIGH IMPEDANCE

Notes:

22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance

and for data to be placed on the bus for the required tSD.

23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.

Document #: 38-06002 Rev. *D

Page 9 of 19

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