CY7C130 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C130

1K x 8 Dual-Port Static RAM

Cypress Semiconductor 

CY7C130/CY7C131

CY7C140/CY7C141

Switching Waveforms

Read Cycle No. 1[19, 20]

ADDRESS

DATA OUT

tOHA

PREVIOUS DATAVALID

Either Port Address Access

tRC

tAA

DATA VALID

Read Cycle No. 2[19, 21]

CE

OE

DATA OUT

tPU

ICC

ISB

Read Cycle No. 3[20]

Either Port CE/OE Access

tACE

tLZOE

tLZCE

tDOE

tHZOE

DATA VALID

tHZCE

tPD

ADDRESSR

R/WR

DINR

Read with BUSY, Master: CY7C130 and CY7C131

tRC

ADDRESS MATCH

tPWE

tHD

VALID

ADDRESSL

BUSYL

DOUTL

tPS

tBLA

ADDRESS MATCH

tBHA

tBDD

tWDD

tDDD

Notes:

19. R/W is HIGH for read cycle.

20. Device is continuously selected, CE = VIL and OE = VIL.

21. Address valid prior to or coincident with CE transition LOW.

VALID

Document #: 38-06002 Rev. *D

Page 8 of 19

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