CXB1810FN 데이터 시트보기 (PDF) - Sony Semiconductor

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CXB1810FN

Post Amplifier for Optical Fiber Communication Receiver

Sony Semiconductor 

CXB1810FN

2. Alarm block

In this block, the input signal amplitude is detected and the signal interruption alarm is output when the

amplitude becomes lower than the set alarm level. The alarm level setting can be adjusted by connecting an

external resistor Rd between the DOWN and VCC pins.

Also, this IC can set the maximum identification voltage amplitude to two levels. The maximum identification

voltage amplitude is set to 50mVp-p (single ended) when the SW pin is open or high level, or to 15mVp-p

(single ended) when the SW pin is low level.

Figs. 15 and 16 show the relation of Rd and the alarm assert/deassert level. Setting the SW pin to low level is

recommended when Rd is 510Ω or less.

High level

VDAS → Deassert level

VAS → Assert level

SW → Low

SW → High

Low level

VDAS

VAS

3dB

3dB

Hysteresis

Fig. 3

15

50

Input voltage (mVp-p, single phase)

Fig. 4

In addition, the SD response deassert time is guaranteed only under the conditions noted in the AC Electrical

Characteristics item, but the response becomes delayed as the input signal amplitude becomes larger. This is

because the input resistor R1 shown in Fig. 1 is small at 50Ω, so the charge accumulated in C2 is relatively

large and the discharge time for this charge accounts for most of the SD response deassert time. The SD

response deassert time can be shortened by using the external circuit shown in Fig. 5 or by shorting the CAP1

and CAP1B pins. However, care should be taken as the auto-offset canceler circuit does not operate in this

case causing the reception sensitivity to deteriorate. Fig. 14 shows the relation between the SD response

deassert time and the electrical input amplitude when using the connection shown in Fig. 5.

C1

15

100Ω

C1

14

1.5kΩ

12

C2

1.5kΩ

11

R1

R1

R2

R2

Fig. 5

– 10 –

To inside the IC

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