CXB1810FN
3. Substrate layout
The exposed metal portions on the rear surface of the package used for the CXB1810FN are electrically
connected to the silicon substrate. Superior thermal radiation characteristics can be obtained by connecting
the rear surface of the package and these exposed metal portions to the ground surface on the PCB.
Providing lands directly below the package as shown in the figure below and connecting as many thermal vias
as possible to the inner layer ground surface is recommended.
0.4mm
0.25mm
1.45mm 0.75mm 2.0mm
4. Other
• Be careful when handling this IC as its electrostatic discharge strength is weak.
• Be sure to connect all power supply pins (VCCO, VCC) and ground pins (VEEO, VEE) to power supplies or
grounds, respectively. For example, if only VCCO is left open and power is supplied to the other pin, the IC
may malfunction.
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