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CMX882

FRS Signalling Processor

CML Microsystems Plc 

FRS Signalling Processor

CMX882

1.5.1 Sleep Mode and Auto Start Up

Power-on reset or C-BUS general reset places the CMX882 into sleep mode, which results in all internal

blocks, except the xtal clock circuit, being placed in power-saved mode. The xtal clock circuit can be

power-saved but this must be done by an explicit C-BUS command. Power saving is achieved by turning

off bias current sources or disabling local clocks, as appropriate.

During system standby periods, parts of the device can be put into sleep mode by the host to conserve

power. The Auxiliary ADC can be programmed so that when the level exceeds a threshold, an interrupt

is issued over the C-BUS and the selected mode (Tx or Rx) “woken up” within 400µs. If this time is too

long to ensure no part of the signal is lost, the DISC or MIC input and ADC path can be kept powered up

whilst in standby mode. The receive modes and transmit modes can also be activated by commands

from the C-BUS. On wake up, activation of the various signal path stages are phased appropriately to

avoid causing unwanted transients. More details are provided in section 1.6.4 on Signal Routing.

The CMX882 can be programmed to wake up its receive path automatically (automatic start-up) when the

DISC input level exceeds the ‘high’ level threshold. While the CMX882 is in automatic receive start-up

mode the DISC input must also be selected for the signal path. When not in automatic start-up mode it is

recommended that the required input is selected during Auxiliary ADC operation to avoid subsequent

switching of the input signal source.

1.5.2 Auxiliary ADC

This section of the CMX882 operates in both Tx and Rx modes and can be used to monitor one of 4

signal sources: Sig_Monitor pin, MIC1, Input_2 or DISC inputs. Activity on the selected input will

optionally issue an interrupt if host intervention is required. During idle periods the majority of the

CMX882 can be placed into low power mode. If monitoring ac signals connected to the Sig_Monitor pin

they must be rectified and filtered using passive external circuitry.

The Auxiliary ADC facility comprises an 8-bit ADC, a comparator, an 8-bit result data word and two 8-bit

threshold registers, one defining the ‘Signal high’ level and the other the ‘Signal low’ level. The two

threshold registers are combined into one 16-bit C-BUS register word. The ADC measures the Signal

level at intervals that are set by C-BUS command. It is advised that the interval be set to <125µs while

waiting for a new incoming signal so that the CMX882 and host µC can be powered up and put into the

correct mode in time to avoid missing any part of the signal. The default interval period following a reset

is 20.8µs. Power dissipation of the Auxiliary ADC can be reduced by increasing the conversion interval

time.

The result of the most recent Auxiliary ADC measurement can be read over the C-BUS whenever the

Signal Processing and Aux ADC circuits are powered up.

The Auxiliary ADC compares each conversion result with the values in the ‘Signal high’ or the ‘Signal low’

threshold registers. The CMX882 can, for example, issue an interrupt to the host µC to wake up the

receive path when the Auxiliary ADC input exceeds the ‘high’ level threshold. The CMX882 can also

issue an interrupt to the host µC to indicate a weak or absent signal when it falls below the ‘low’ level

threshold. This provides a user programmable hysteresis facility. The host must ensure that the value in

the ‘low’ register is always less than that of the ‘high’ register. The options for issuing interrupts and for

automatic start-up are selected by C-BUS command.

The Auxiliary ADC options are controlled by the $B2, $B3 and $C0 C-BUS registers.

The Auxiliary ADC requires the Auxiliary ADC, BIAS and Xtal clock to all be enabled in the Power Down

Control register.

 2004 CML Microsystems Plc

16

D/882/7

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