MAX3890ECB 데이터 시트보기 (PDF) - Maxim Integrated

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MAX3890ECB

+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs

Maxim Integrated 

+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer

with Clock Synthesis and LVDS Inputs

PIN

1, 17, 33, 48, 49, 63

2, 5, 7, 10, 13,

14, 32, 56, 60, 64

3

4

6

8

9

11

12

15

NAME

GND

VCC

SLBO-

SLBO+

SOS

SCLKO-

SCLKO+

SDO-

SDO+

PCLKI+

16

18, 20, 22, 24, 26,

28, 30, 34, 36, 38,

40, 42, 44, 46, 50, 52

19, 21, 23, 25, 27,

29, 31, 35, 37, 39,

41, 43, 45, 47, 51, 53

54

PCLKI-

PDI15+ to

PDI0+

PDI15- to

PDI0-

PCLKO+

55

PCLKO-

57

RCLK+

58

RCLK-

59

CLKSET

61

FIL-

62

FIL+

EP

Exposed

Pad

Pin Description

Ground

FUNCTION

+3.3V Supply Voltage

System Loopback Inverting Output. Enabled when SOS is high.

System Loopback Noninverting Output. Enabled when SOS is high.

System Loopback Output Select. System loopback disabled when low.

Inverting PECL Serial Clock Output

Noninverting PECL Serial Clock Output

Inverting PECL Serial-Data Output

Noninverting PECL Serial-Data Output

Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-clock signal to the

PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.

Inverting LVDS Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI

inputs. Note that data is updated on the positive transition of the PCLKI signal.

Noninverting LVDS Parallel Data Inputs. Data is clocked on the PCLKI positive transition.

Inverting LVDS Parallel Data Inputs. Data is clocked on the PCLKI positive transition.

Noninverting LVDS Parallel Clock Output. Use positive transition of PCLKO to clock the

overhead management circuit.

Inverting LVDS Parallel Clock Output. Use positive transition of PCLKO to clock the over-

head management circuit.

Noninverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal refer-

ence clock to the RCLK inputs.

Inverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference

clock to the RCLK inputs.

Reference Clock Rate Programming Pin:

CLKSET = VCC: Reference Clock Rate = 155.52MHz

CLKSET = Open: Reference Clock Rate = 77.76MHz

CLKSET = 20kΩ to GND: Reference Clock Rate = 51.84MHz

CLKSET = GND: Reference Clock Rate = 38.88MHz

Filter Capacitor Input. Connect a 330nF capacitor between FIL+ and FIL-.

Filter Capacitor Input. Connect a 330nF capacitor between FIL+ and FIL-.

Ground. This must be soldered to a circuit board for proper thermal performance (see

Package Information).

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