MAX3890ECB 데이터 시트보기 (PDF) - Maxim Integrated

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MAX3890ECB

+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs

Maxim Integrated 

+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer

with Clock Synthesis and LVDS Inputs

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC = +3.0V to +3.6V, differential LVDS loads = 100Ω ±1%, PECL loads = 50Ω ±1% to (VCC - 2V), CML loads = 50Ω ±1% to VCC,

TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

PROGRAMMING INPUT (CLKSET)

CLKSET Input Current

ICLKSET CLKSET = 0 or VCC

TTL INPUT (SOS)

Input Voltage High

VIH

Input Voltage Low

VIL

Input Current High

IIH

Input Current Low

IIL

CURRENT MODE LOGIC (CML) OUTPUTS (SLBO±)

Differential Output Voltage

|VOD|

Single-Ended Output Resistance

RO

MIN TYP MAX UNITS

±500

µA

2.0

V

0.8

V

-10

10

µA

-10

10

µA

100

400

mV

50

Ω

AC ELECTRICAL CHARACTERISTICS

(VCC = +3.0V to +3.6V, differential LVDS load = 100Ω ±1%, PECL loads = 50Ω ±1% to (VCC - 2V), CML loads = 50Ω ±1% to VCC,

TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Serial Clock Rate

fSCLK

2.488

GHz

Parallel Data Setup Time

tSU (Note 2)

300

ps

Parallel Data-Hold Time

tH

(Note 2)

700

ps

PCLKO to PCLKI Skew

tSKEW Figure 2

0

Output Jitter Generation (SCLKO±)

Jitter bandwidth = 12kHz to 20MHz,

Φ0

RCLK amplitude > |VIDTH| (Note 3)

+4.0

3

ns

psRMS

PECL Differential Output Rise/Fall

Time

tR, tF 20% to 80%

120

ps

Parallel Input Clock Rate

Reference Clock Input (RCLKI)

Rise/Fall Time

fPCLKI

tR, tF

20% to 80%, f = 155.52MHz

155.52

1.0

MHz

ns

Parallel Clock Output (PCLKO)

Rise/Fall Time

tR, tF 20% to 80%

1.0

ns

Serial Clock Output (SCLKO) to

Serial-Data Output (SDO) Delay

tSCLK-SD SCLKO rising edge to SDO edge

110

290

ps

Note 1: AC characteristics guaranteed by design and characterization.

Note 2: Setup and hold times are relative to the rising edge of PCLKI+, measured by applying a 155.52MHz differential parallel

clock with rise/fall time = 1ns (20% to 80%). See Figure 2.

Note 3: For fRCLK = 38.88MHz, the minimum reference clock amplitude is ≥ 200mV.

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