7411(2017) 데이터 시트보기 (PDF) - Analog Devices
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7411
(Rev.:2017)
(Rev.:2017)
Analog Devices
7411 Datasheet PDF : 36 Pages
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Data Sheet
ADT7411
Parameter1
POWER REQUIREMENTS
VDD
VDD Settling Time
IDD (Normal Mode)8
IDD (Power-Down Mode)
Power Dissipation
Min Typ Max Unit
2.7
5.5
V
50
ms
3
mA
2.2
3
mA
10
µA
10
µA
10
mW
33
µW
Conditions/Comments
VDD settles to within 10% of its final voltage level.
VDD = 3.3 V, VIH = VDD and VIL = GND.
VDD = 5 V, VIH = VDD and VIL = GND.
VDD = 3.3 V, VIH = VDD and VIL = GND.
VDD = 5 V, VIH = VDD and VIL = GND.
VDD = 3.3 V. Using normal mode.
VDD = 3.3 V. Using shutdown mode.
1 See the Terminology section.
2 Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, AIN4, AIN5,
AIN6, AIN7, and AIN8.
3 Guaranteed by design and characterization, not production tested.
4 The SDA and SCL timing is measured with the input filters turned on so as to meet the fast-mode I2C specification. Switching off the input filters improves the transfer
rate but has a negative effect on the EMC behavior of the part.
5 Guaranteed by design. Not tested in production.
6 The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns.
7 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V.
8 IDD specification is valid for full-scale analog input voltages. Interface inactive. ADC active. Load currents excluded.
t1
SCL
t4
t2
SDA
DATA IN
t3
SDA
DATA OUT
Figure 2. I2C Bus Timing Diagram
t5
t6
t7
CS
t1
t2
t7
SCLK
DIN
t3
t5
t6
D7 D6 D5 D4 D3 D2 D1 D0 X
X
X
X
X
X
X
X
DOUT
t4
t8
X
X
X
X
X
X
X
X D7 D6 D5 D4 D3 D2 D1
D0
Figure 3. SPI Bus Timing Diagram
200µA
IOL
TO
OUTPUT
PIN CL
50pF
1.6V
200µA
IOH
Figure 4. Load Circuit for Access Time and Bus Relinquish Time
Rev. C | Page 5 of 36
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