ADSP-21469KBZ-ENG2 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21469KBZ-ENG2

SHARC Processor

Analog Devices 

ADSP-21469/ADSP-21469W

• Four precision clock generators

• Input data port/parallel data acquisition port

• Four stereo asynchronous sample rate converters

The ADSP-21469 processor also contains a 14 lead digital

peripheral interface, which controls:

• Two general-purpose timers

• Two serial peripheral interfaces

• One universal asynchronous receiver/transmitter (UART)

• An I2C®-compatible 2-wire interface

• Two PCGs (C and D) can also be routed through DPI

DMA Controller

The ADSP-21469’s on-chip DMA controller allows data trans-

fers without processor intervention. The DMA controller

operates independently and invisibly to the processor core,

allowing DMA operations to occur while the core is simulta-

neously executing its program instructions. DMA transfers can

occur between the ADSP-21469’s internal memory and its serial

ports, the SPI-compatible (serial peripheral interface) ports, the

IDP (input data port), the parallel data acquisition port (PDAP)

or the UART.

Thirty-six channels of DMA are available on the ADSP-21469,

16 via the serial ports, eight via the input data port, two for the

UART, two for the SPI interface, two for the external port, two

for memory-to-memory transfers, two for the link port, two for

the FFT/IIR/FIR accelerator.

Programs can be downloaded to the ADSP-21469 using DMA

transfers. Other DMA features include interrupt generation

upon completion of DMA transfers, and DMA chaining for

automatic linked DMA transfers.

Delay Line DMA

The ADSP-21469 processor provides delay line DMA function-

ality. This allows processor reads and writes to external delay

line buffers (and hence to external memory) with limited core

interaction.

Scatter/Gather DMA

The ADSP-21469 processor provides scatter/gather DMA

functionality.

This allows processor DMA reads/writes to/from non-contin-

geous memory blocks.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to

connect various peripherals to any of the DSP DAI pins

(DAI_P20–1).

Programs make these connections using the signal routing unit

(SRU), shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

Preliminary Technical Data

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

The DAI also includes eight serial ports, four precision clock

generators (PCG), S/PDIF transceiver, four ASRCs, and an

input data port (IDP). The IDP provides an additional input

path to the ADSP-21469 core, configurable as either eight chan-

nels of serial data, or a single 20-bit wide synchronous parallel

data acquisition port. Each data channel has its own DMA

channel that is independent from the ADSP-21469’s serial ports.

Serial Ports

The ADSP-21469 features eight synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

Serial ports can support up to 16 transmit or 16 receive channels

of audio data when all eight SPORTs are enabled, or four full

duplex TDM streams of 128 channels per frame.

The serial ports operate at a maximum data rate of 56.25 Mbps.

Serial port data can be automatically transferred to and from

on-chip memory/external memory via dedicated DMA chan-

nels. Each of the serial ports can work in conjunction with

another serial port to provide TDM support. One SPORT pro-

vides two transmit signals while the other SPORT provides the

two receive signals. The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

• I2S mode

• Packed I2S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Each of the serial ports supports the left-justified sample pair

and I2S protocols (I2S is an industry-standard interface com-

monly used by audio codecs, ADCs, and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pair or I2S channels (using two stereo

devices) per serial port, with a maximum of up to 32 I2S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I2S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional μ-law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

Rev. PrB | Page 8 of 56 | November 2008

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