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ADSP-21469KBZ-ENG2

SHARC Processor

Analog Devices 

ADSP-21469/ADSP-21469W

GENERAL DESCRIPTION

The ADSP-21469 SHARC® processor is a member of the SIMD

SHARC family of DSPs that feature Analog Devices' Super Har-

vard Architecture. The ADSP-21469 is source code compatible

with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-

2116x DSPs as well as with first generation ADSP-2106x

SHARC processors in SISD (single-instruction, single-data)

mode. The ADSP-21469 is a 32-bit/40-bit floating point proces-

sors optimized for high performance audio applications with its

large on-chip SRAM, multiple internal buses to eliminate I/O

bottlenecks, and an innovative digital applications interface

(DAI).

Table 1. SHARC Features

Feature

Frequency

Core

Internal RAM

DDR2 Memory Interface

DDR2 Memory Bus Width

Direct DMA from SPORTs to external

memory

FFT accelerator

FIR accelerator

IIR accelerator

IDP

Serial Ports

ASRC (channels)

UART

DAI and DPI

Link Ports

S/PDIF transceiver

AMI interface with 8-bit support

SPI

TWI

Package

Description

450 MHz

5-stage pipeline

5 Mbits

1/2 CCLK Max

16-bits

Yes

Yes

Yes

Yes

Yes

8

8

1

20/14 pins

2

1

Yes

2

1

324-ball,

19 mm x 19 mm PBGA

As shown in the functional block diagram on Page 1, the

ADSP-21469 uses two computational units to deliver a signifi-

cant performance increase over the previous SHARC processors

on a range of DSP algorithms. Fabricated in a state-of-the-art,

high speed, CMOS process, the ADSP-21469 processor achieves

an instruction cycle time of 2.22 ns at 450 MHz. With its SIMD

computational hardware, the ADSP-21469 can perform

2.7 GFLOPS.

Preliminary Technical Data

Table 2 shows performance benchmarks for the ADSP-21469.

Table 2. Processor Benchmarks

Benchmark Algorithm

Speed

(at 450 MHz)

1024 Point Complex FFT (Radix 4, With Reversal) 20.44 μs

FIR Filter (per Tap)1

1.11 ns

IIR Filter (per Biquad)1

4.43 ns

Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1]

[4 × 4] × [4 × 1]

10.0 ns

17.78 ns

Divide (y/×)

6.67 ns

Inverse Square Root

10.0 ns

1 Assumes two files in multichannel SIMD mode

The ADSP-21469 continues SHARC’s industry-leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features.

The block diagram of the ADSP-21469 on Page 1 illustrates the

following architectural features:

• Two processing elements, each of which comprises an

ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

• Two programmable interval timers with external event

counter capabilities

• On-chip SRAM

• JTAG test access port

The block diagram of the ADSP-21469 on Page 1 also illustrates

the following architectural features:

• DMA controller

• Digital applications interface that includes four precision

clock generators (PCG), an S/PDIF-compatible digital

audio receiver/transmitter with four independent asyn-

chronous sample rate converters, an input data port (IDP)

with eight serial ports, eight serial interfaces, a 20-bit paral-

lel input port (PDAP), and a flexible signal routing unit

(DAI SRU).

• Digital peripheral interface that includes two timers, one

UART, two serial peripheral interfaces (SPI), a 2-wire

interface (TWI), and a flexible signal routing unit

(DPI SRU).

Rev. PrB | Page 4 of 56 | November 2008

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