ADSP-21469KBZ-ENG2 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21469KBZ-ENG2

SHARC Processor

Analog Devices 

ADSP-21469/ADSP-21469W

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

mid-point of the PWM period. In double update mode, a sec-

ond updating of the PWM registers is implemented at the mid-

point of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis-

tortion in three-phase PWM inverters.

Link Ports

Two 8-bit wide link ports can connect to the link ports of other

DSPs or peripherals. Link ports are bidirectional ports having

eight data lines, an acknowledge line and a clock line. Link ports

can operate at a maximum frequency of 166 MHz.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues.

Program Booting

The internal memory of the ADSP-21469 boots at system

power-up from an 8-bit EPROM via the external port, link port,

an SPI master, or an SPI slave. Booting is determined by the

boot configuration (BOOTCFG2–0) pins (see Table 8 on

Page 15).

The “Running Reset” feature allows a user to perform a reset of

the processor core and peripherals, but without resetting the

PLL and DDR2 DRAM controller, or performing a Boot. The

functionality of the CLKOUT/RESETOUT/RUNRSTIN pin has

now been extended to also act as the input for initiating a Run-

ning Reset. For more information, see the ADSP-2146x SHARC

Processor Hardware Reference.

Power Supplies

The processors have separate power supply connections for the

internal (VDD_INT), external (VDD_EXT), and analog

(VDD_A/VSS_A) power supplies. The internal and analog supplies

must meet the VDD_INT specifications. The external supply must

meet the VDD_EXT specification. All external supply pins must

be connected to the same power supply.

Preliminary Technical Data

Note that the analog supply pin (VDD_A) powers the processor’s

internal clock generator PLL. To produce a stable clock, it is rec-

ommended that PCB designs use an external filter circuit for the

VDD_A pin. Place the filter components as close as possible to

the VDD_A/VSS_A pins. For an example circuit, see Figure 2. (A

recommended ferrite chip is the muRata BLM18AG102SN1D).

VDDINT

100nF

10nF

1nF

ADSP-21469

VDD_A

HI Z FERRITE

BEAD CHIP

VSS_A

LOCATE ALL COMPONENTS

CLOSE TO VDD_A AND VSS_A PINS

Figure 2. Analog Power (VDD_A) Filter Circuit

To reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for VDD_INT and VSS. Use wide traces

to connect the bypass capacitors to the analog power (VDD_A)

and ground (VSS_A) pins. Note that the VDD_A and VSS_A pins

specified in Figure 2 are inputs to the processor and not the ana-

log ground plane on the board—the VSS_A pin should connect

directly to digital ground (VSS) at the chip

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21469 pro-

cessor to monitor and control the target board processor during

emulation. Analog Devices DSP Tools product line of JTAG

emulators provides emulation at full processor speed, allowing

inspection and modification of memory, registers, and proces-

sor stacks. The processor's JTAG interface ensures that the

emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User's Guide”.

DEVELOPMENT TOOLS

The ADSP-21469 processor is supported with a complete set of

CROSSCORE® software and hardware development tools,

including Analog Devices emulators and VisualDSP++® devel-

opment environment. The same emulator hardware that

supports other SHARC processors also fully emulates the

ADSP-21469 processor.

EZ-KIT Lite Evaluation Board

For evaluation of the processors, use the EZ-KIT Lite® board

being developed by Analog Devices. The board comes with on-

chip emulation capabilities and is equipped to enable software

development. Multiple daughter cards are available.

Rev. PrB | Page 10 of 56 | November 2008

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