AD7679(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD7679 Datasheet PDF : 28 Pages
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AD7679
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
AGND 1
AVDD 2
MODE0 3
MODE1 4
D0/OB/2C 5
NC 6
NC 7
D1/A0 8
D2/A1 9
D3 10
D4/DIVSCLK[0] 11
D5/DIVSCLK[1] 12
PIN 1
IDENTIFIER
AD7679
TOP VIEW
(Not to Scale)
36 AGND
35 CNVST
34 PD
33 RESET
32 CS
31 RD
30 DGND
29 BUSY
28 D17
27 D16
26 D15
25 D14
NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24
03085–0–004
Figure 4. 48-Lead LQFP(ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 44
AGND
P
Analog Power Ground Pin.
2, 47
AVDD
P
Input Analog Power Pins. Nominally 5 V.
3
MODE0
DI
Data Output Interface Mode Selection.
4
MODE1
DI
Data Output Interface Mode Selection:
Interface MODE MODE1 MODE0 Description
0
0
0
18-Bit Interface
1
0
1
16-Bit Interface
2
1
0
Byte Interface
3
1
1
Serial Interface
5
D0/OB/2C
DI/O When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the
data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos
complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is
inverted, resulting in a twos complement output from its internal shift register.
6, 7, 40– NC
42, 45
No Connect.
8
D1/A0
DI/O When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all
other modes, this input pin controls the form in which data is output, as shown in Table 7.
9
D2/A1
DI/O When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output
bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7.
10
D3
DO
In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin
is always an output, regardless of the interface mode.
11, 12 D[4:5]or
DI/O In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
DIVSCLK[0:1]
When MODE = 3 (serial mode), EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after
convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock
that clocks the data output. In other serial modes, these pins are not used.
13
D6
DI/O In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus.
or EXT/INT
When MODE = 3 (serial mode), this input, part of the serial port, is used as a digital select input for
choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is
selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an
external clock signal connected to the SCLK input.
Rev. 0 | Page 8 of 28
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