AD7679(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD7679 Datasheet PDF : 28 Pages
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AD7679
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter
Symbol Min
Refer to Figure 32 and Figure 33
Convert Pulsewidth
Time between Conversions
CNVST LOW to BUSY HIGH Delay
t1
10
t2
1.75
t3
BUSY HIGH All Modes Except Master Serial Read after Convert
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
Refer to Figure 34, Figure 35, and Figure 36 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay
t4
t5
t6
10
t7
t8
250
t9
10
t10
Data Valid to BUSY LOW Delay
Bus Access Request to Data Valid
Bus Relinquish Time
Refer to Figure 38 and Figure 39 (Master Serial Interface Modes) 1
CS LOW to SYNC Valid Delay
t11
20
t12
t13
5
t14
CS LOW to Internal SCLK Valid Delay
t15
CS LOW to SDOUT Delay
t16
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay2
Internal SCLK Period2
Internal SCLK HIGH2
Internal SCLK LOW2
SDOUT Valid Setup Time2
SDOUT Valid Hold Time2
SCLK Last Edge to SYNC Delay2
CS HIGH to SYNC HI-Z
t17
t18
3
t19
25
t20
12
t21
7
t22
4
t23
2
t24
3
t25
CS HIGH to Internal SCLK HI-Z
t26
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert2
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
Refer to Figure 40 and Figure 41 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t27
t28
t29
t30
t31
5
t32
3
t33
5
t34
5
t35
25
t36
10
t37
10
Typ
2
525
See Table 4
1.5
25
Max Unit
ns
µs
35
ns
1.5 µs
ns
ns
1.5 µs
ns
ns
1.5 µs
ns
45
ns
15
ns
10
ns
10
ns
10
ns
ns
ns
40
ns
ns
ns
ns
ns
ns
10
ns
10
ns
10
ns
µs
ns
ns
18
ns
ns
ns
ns
ns
ns
1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode.
Rev. 0 | Page 5 of 28
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