AD7641ASTRL 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

일치하는 목록

AD7641ASTRL

18-Bit, 2 MSPS SAR ADC

Analog Devices 

AD7641

APPPLICATIONS INFORMATION

IN+

REF

REFGND

MSB

131,072C 65,536C

131,072C 65,536C

MSB

IN–

4C

2C

4C

2C

AGND

LSB SW+

SWITCHES

CONTROL

C

C

COMP

C

C

SW–

LSB

CONTROL

LOGIC

BUSY

OUTPUT

CODE

CNVST

AGND

Figure 21. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7641 is a very fast, low power, single-supply, precise

18-bit ADC using successive approximation architecture. The

AD7641 features different modes to optimize performances

according to the applications. In warp mode, the AD7641 is

capable of converting 2,000,000 samples per second (2 MSPS).

The AD7641 provides the user with an on-chip track-and-hold,

successive approximation ADC that does not exhibit any

pipeline or latency, making it ideal for multiple multiplexed

channel applications.

The AD7641 can operate from a single 2.5 V supply and

interface to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed

in a 48-lead LQFP package or a tiny 48-lead LFCSP package,

which combines space savings with flexibility and allows the

AD7641 to be configured as either a serial or a parallel

interface. The AD7641 is pin-to-pin-compatible and is a

speed upgrade of the AD7674, AD7678, and AD7679.

CONVERTER OPERATION

The AD7641 is a successive approximation ADC based on a

charge redistribution DAC. Figure 21 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary weighted capacitors that are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

comparator’s input are connected to AGND via SW+ and SW−.

All independent switches are connected to the analog inputs.

Therefore, the capacitor arrays are used as sampling capacitors

and acquire the analog signal on the IN+ and IN− inputs. A

conversion phase is initiated once the acquisition phase is complete

and the CNVST input goes low. When the conversion phase

begins, SW+ and SW− are opened first. The two capacitor

arrays are then disconnected from the inputs and connected to

the REFGND input. Therefore, the differential voltage between

the inputs (IN+ and IN−) captured at the end of the acquisition

phase is applied to the comparator inputs, causing the

comparator to become unbalanced. By switching each element

of the capacitor array between REFGND and REF, the comparator

input varies by binary weighted voltage steps (VREF/2, VREF/4

throughVREF/131072). The control logic toggles these switches,

starting with the MSB first, to bring the comparator back into a

balanced condition. After the completion of this process, the

control logic generates the ADC output code and brings BUSY

output low.

MODES OF OPERATION

The AD7641 features three modes of operations: wideband

warp, warp, and normal. Each of these modes is more suitable

for specific applications.

The wideband warp (WARP = high, NORMAL = high) and

warp (WARP = high, NORMAL = low) modes allow the fastest

conversion rate of up to 2 MSPS. However, in these modes, the

full specified accuracy is guaranteed only when the time between

conversions does not exceed 1 ms. If the time between two

consecutive conversions is longer than 1 ms (for instance after

power-up), the first conversion result should be ignored. These

modes make the AD7641 ideal for applications where both high

accuracy and fast sample rates are required. Wideband warp

mode offers slightly improved linearity and THD over warp mode.

Normal mode (NORMAL = low, WARP = low) is the fastest

mode (1.5 MSPS) without any limitation on time between

conversions. This mode makes the AD7641 ideal for

asynchronous applications, such as data acquisition systems,

where both high accuracy and fast sample rates are required.

Rev. 0 | Page 15 of 28

Share Link: