AD6623S/PCB(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD6623S/PCB
(Rev.:Rev0)

4-Channel, 104 MSPS Digital Transmit Signal Processor (TSP)

Analog Devices 

TIMING DIAGRAMS—INM MICROPORT MODE

CLK

RD (DS)

tSC

WR (RW)

tHC

tHWR

CS

A[2:0]

tSAM

tHAM

VALID ADDRESS

D[7:0]

RDY

(DTACK)

tSAM

tHAM

VALID DATA

tDRDY

tACC

NOTES

1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS

MEASURED FROM FE OF WR TO THE RE OF RDY.

2. tACC REQUIRES A MAXIMUM 9 CLK PERIODS.

Figure 12. INM Microport Write Timing Requirements

AD6623

TIMING DIAGRAMS—MNM MICROPORT MODE

CLK

DS (RD)

RW (WR)

tSC

tHDS

tHC

tHRW

CS

A[2:0]

D[7:0]

tSAM

tHAM

VALID ADDRESS

tSAM

tHAM

VALID DATA

DTACK

(RDY)

tACC

tDDTACK

NOTES

1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS

MEASURED FROM FE OF DS TO THE FE OF DTACK.

2. tACC REQUIRES A MAXIMUM 9 CLK PERIODS.

Figure 14. MNM Microport Write Timing Requirements

CLK

tSC

tHC

RD (DS)

WR (RW)

CS

A[2:0]

tSAM

VALID ADDRESS

tZD

D[7:0]

tDD

tHAM

tZD

VALID DATA

tDRDY

RDY

(DTACK)

tACC

NOTES

1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS

TIME IS MEASURED FROM FE OF WR TO THE RE OF RDY.

2. tACC REQUIRES A MAXIMUM OF 13 CLK PERIODS AND APPLIES TO

A[2:0] = 7, 6, 5, 3, 2, 1

Figure 13. INM Microport Read Timing Requirements

CLK

tHC

tSC

tHDS

DS (RD)

RW (WR)

CS

A[2:0]

tSAM

VALID ADDRESS

tZD

tDD

tHAM

tZD

D[7:0]

VALID DATA

DTACK

(RDY)

tACC

tDDTACK

NOTES

1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS

MEASURED FROM FE OF DS TO THE FE OF DTACK.

2. tACC REQUIRES A MAXIMUM 13 CLK PERIODS.

Figure 15. Motorola Microport Read Timing Requirements

REV. 0

–9–

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