AD6623
SCLK
SDFO
SDIN
tDSFO0A
tSSDI0
DATAn
tHSDI0
Figure 8. Serial Port Timing, Master Mode (SCS = 0), Channel is Self-Framing
SCLK
SDFO
SDIN
tDSFO1
tSSDI1
DATAn
tHSDI1
Figure 9. Serial Port Timing, Slave Mode (SCS = 1), Channel is Self-Framing
SCLK
SDFO
SDFI
SDIN
tDSFO0B
nCLKs
tSSFI0
tHSFI0
tSSDI0
tHSDI0
DATAn
Figure 10. Serial Port Timing, Master Mode (SCS = 0), Channel is External-Framing
SCLK
SDFO
SDFI
SDIN
tDSFO1
nCLKs
tSSFI1
tHSFI1
tSSDI1
DATAn
tHSDI1
Figure 11. Serial Port Timing, Slave Mode (SCS = 1), Channel is External-Framing
–8–
REV. 0