AD6623S/PCB(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD6623S/PCB Datasheet PDF : 40 Pages
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GENERAL TIMING CHARACTERISTICS1, 2
Parameter (Conditions)
Temp
Test
Level
AD6623AS
Min Typ Max
CLK Timing Requirements:
tCLK
tCLKL
tCLKH
CLK Period
CLK Width Low
CLK Width High
RESET Timing Requirement:
tRESL
RESET Width Low
Full
I
9.6
Full
IV
3
Full
IV
3
Full
I
30.0
Input Data Timing Requirements:
tSI
INOUT[17:0], QIN to ↑CLK Setup Time
Full
IV
1
tHI
INOUT[17:0], QIN to ↑CLK Hold Time
Full
IV
2
Output Data Timing Characteristics:
tDO
↑CLK to OUT[17:0], INOUT[17:0],
QOUT Output Delay Time
tDZO
OEN HIGH to OUT[17:0] Active
Full
IV
2
Full
IV
3
SYNC Timing Requirements:
tSS
SYNC(0, 1, 2, 3) to ↑CLK Setup Time
tHS
SYNC(0, 1, 2, 3) to ↑CLK Hold Time
Full
IV
1
Full
IV
2
Master Mode Serial Port Timing Requirements (SCS = 0):
Switching Characteristics3
tDSCLK1
tDSCLKH
tDSCLKL
↑CLK to ↑SCLK Delay (divide by 1)
Full
IV
4
↑CLK to ↑SCLK Delay (for any other divisor) Full
IV
5
↑CLK to ↓SCLK Delay
(divide by 2 or even number)
Full
IV
3.5
tDSCLKLL
↓CLK to ↓SCLK Delay
(divide by 3 or odd number)
Full
IV
4
Channel is Self-Framing
tSSDI0
tHSDI0
tDSFO0A
SDIN to ↑SCLK Setup Time
SDIN to ↑SCLK Hold Time
↑SCLK to SDFO Delay
Channel is External-Framing
Full
IV
1.7
Full
IV
0
Full
IV
0.5
tSSFI0
tHSFI0
tSSDI0
tHSDI0
tDSFO0B
SDFI to ↑SCLK Setup Time
SDFI to ↑SCLK Hold Time
SDIN to ↑SCLK Setup Time
SDIN to ↑SCLK Hold Time
↑SCLK to SDFO Delay
Full
IV
2
Full
IV
0
Full
IV
2
Full
IV
0
Full
IV
0.5
Slave Mode Serial Port Timing Requirements (SCS = 1):
Switching Characteristics3
tSCLK
tSCLKL
tSCLKH
SCLK Period
SCLK Low Time
SCLK High Time
Channel is Self-Framing
Full
IV
Full
IV
3.5
Full
IV
3.5
tSSDH
tHSDH
tDSFO1
SDIN to ↑SCLK Setup Time
SDIN to ↑SCLK Hold Time
↑SCLK to SDFO Delay
Channel is External-Framing
Full
IV
1
Full
IV
2.5
Full
IV
4
tSSFI1
tHSFI1
tSSDI1
tHSDI1
tDSFO1
SDFI to ↑ SCLK Setup Time
SDFI to ↑SCLK Hold Time
SDIN to ↑SCLK Setup Time
SDIN to ↑SCLK Hold Time
↓SCLK to SDFO Delay
Full
IV
2
Full
IV
1
Full
IV
1
Full
IV
2.5
Full
IV
10
NOTES
1All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.
2CLOAD = 40 pF on all outputs (unless otherwise specified).
3The timing parameters for SCLK, SDIN, SDFI, SDFO, and SYNC apply to all four channels (A, B, C, and D).
Specifications subject to change without notice.
0.5 × tCLK
6
7.5
10.5
13
9
10
3.5
3
2 ؋ tCLK
10
AD6623
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0
–5–
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